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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
184 lines
5.6 KiB
C
184 lines
5.6 KiB
C
/*
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* (C) Copyright 2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Author: Igor Lisitsin <igor@emcraft.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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/*
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* SPR test
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*
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* The test checks the contents of Special Purpose Registers (SPR) listed
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* in the spr_test_list array below.
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* Each SPR value is read using mfspr instruction, some bits are masked
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* according to the table and the resulting value is compared to the
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* corresponding table value.
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*/
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#include <post.h>
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#if CONFIG_POST & CONFIG_SYS_POST_SPR
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#include <asm/processor.h>
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#ifdef CONFIG_4xx_DCACHE
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#include <asm/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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static struct {
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int number;
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char * name;
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unsigned long mask;
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unsigned long value;
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} spr_test_list [] = {
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/* Standard Special-Purpose Registers */
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{0x001, "XER", 0x00000000, 0x00000000},
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{0x008, "LR", 0x00000000, 0x00000000},
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{0x009, "CTR", 0x00000000, 0x00000000},
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{0x016, "DEC", 0x00000000, 0x00000000},
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{0x01a, "SRR0", 0x00000000, 0x00000000},
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{0x01b, "SRR1", 0x00000000, 0x00000000},
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{0x110, "SPRG0", 0x00000000, 0x00000000},
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{0x111, "SPRG1", 0x00000000, 0x00000000},
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{0x112, "SPRG2", 0x00000000, 0x00000000},
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{0x113, "SPRG3", 0x00000000, 0x00000000},
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{0x11f, "PVR", 0x00000000, 0x00000000},
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/* Additional Special-Purpose Registers.
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* The values must match the initialization
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* values from arch/powerpc/cpu/ppc4xx/start.S
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*/
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{0x30, "PID", 0x00000000, 0x00000000},
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{0x3a, "CSRR0", 0x00000000, 0x00000000},
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{0x3b, "CSRR1", 0x00000000, 0x00000000},
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{0x3d, "DEAR", 0x00000000, 0x00000000},
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{0x3e, "ESR", 0x00000000, 0x00000000},
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#ifdef CONFIG_440
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{0x3f, "IVPR", 0xffff0000, 0x00000000},
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#endif
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{0x100, "USPRG0", 0x00000000, 0x00000000},
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{0x104, "SPRG4", 0x00000000, 0x00000000},
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{0x105, "SPRG5", 0x00000000, 0x00000000},
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{0x106, "SPRG6", 0x00000000, 0x00000000},
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{0x107, "SPRG7", 0x00000000, 0x00000000},
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{0x10c, "TBL", 0x00000000, 0x00000000},
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{0x10d, "TBU", 0x00000000, 0x00000000},
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#ifdef CONFIG_440
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{0x11e, "PIR", 0x0000000f, 0x00000000},
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#endif
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{0x130, "DBSR", 0x00000000, 0x00000000},
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{0x134, "DBCR0", 0x00000000, 0x00000000},
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{0x135, "DBCR1", 0x00000000, 0x00000000},
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{0x136, "DBCR2", 0x00000000, 0x00000000},
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{0x138, "IAC1", 0x00000000, 0x00000000},
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{0x139, "IAC2", 0x00000000, 0x00000000},
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{0x13a, "IAC3", 0x00000000, 0x00000000},
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{0x13b, "IAC4", 0x00000000, 0x00000000},
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{0x13c, "DAC1", 0x00000000, 0x00000000},
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{0x13d, "DAC2", 0x00000000, 0x00000000},
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{0x13e, "DVC1", 0x00000000, 0x00000000},
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{0x13f, "DVC2", 0x00000000, 0x00000000},
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{0x150, "TSR", 0x00000000, 0x00000000},
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{0x154, "TCR", 0x00000000, 0x00000000},
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#ifdef CONFIG_440
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{0x190, "IVOR0", 0x0000fff0, 0x00000100},
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{0x191, "IVOR1", 0x0000fff0, 0x00000200},
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{0x192, "IVOR2", 0x0000fff0, 0x00000300},
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{0x193, "IVOR3", 0x0000fff0, 0x00000400},
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{0x194, "IVOR4", 0x0000fff0, 0x00000500},
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{0x195, "IVOR5", 0x0000fff0, 0x00000600},
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{0x196, "IVOR6", 0x0000fff0, 0x00000700},
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{0x197, "IVOR7", 0x0000fff0, 0x00000800},
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{0x198, "IVOR8", 0x0000fff0, 0x00000c00},
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{0x199, "IVOR9", 0x00000000, 0x00000000},
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{0x19a, "IVOR10", 0x0000fff0, 0x00000900},
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{0x19b, "IVOR11", 0x00000000, 0x00000000},
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{0x19c, "IVOR12", 0x00000000, 0x00000000},
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{0x19d, "IVOR13", 0x0000fff0, 0x00001300},
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{0x19e, "IVOR14", 0x0000fff0, 0x00001400},
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{0x19f, "IVOR15", 0x0000fff0, 0x00002000},
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#endif
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{0x23a, "MCSRR0", 0x00000000, 0x00000000},
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{0x23b, "MCSRR1", 0x00000000, 0x00000000},
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{0x23c, "MCSR", 0x00000000, 0x00000000},
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{0x370, "INV0", 0x00000000, 0x00000000},
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{0x371, "INV1", 0x00000000, 0x00000000},
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{0x372, "INV2", 0x00000000, 0x00000000},
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{0x373, "INV3", 0x00000000, 0x00000000},
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{0x374, "ITV0", 0x00000000, 0x00000000},
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{0x375, "ITV1", 0x00000000, 0x00000000},
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{0x376, "ITV2", 0x00000000, 0x00000000},
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{0x377, "ITV3", 0x00000000, 0x00000000},
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{0x378, "CCR1", 0x00000000, 0x00000000},
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{0x390, "DNV0", 0x00000000, 0x00000000},
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{0x391, "DNV1", 0x00000000, 0x00000000},
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{0x392, "DNV2", 0x00000000, 0x00000000},
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{0x393, "DNV3", 0x00000000, 0x00000000},
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{0x394, "DTV0", 0x00000000, 0x00000000},
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{0x395, "DTV1", 0x00000000, 0x00000000},
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{0x396, "DTV2", 0x00000000, 0x00000000},
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{0x397, "DTV3", 0x00000000, 0x00000000},
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#ifdef CONFIG_440
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{0x398, "DVLIM", 0x0fc1f83f, 0x0001f800},
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{0x399, "IVLIM", 0x0fc1f83f, 0x0001f800},
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#endif
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{0x39b, "RSTCFG", 0x00000000, 0x00000000},
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{0x39c, "DCDBTRL", 0x00000000, 0x00000000},
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{0x39d, "DCDBTRH", 0x00000000, 0x00000000},
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{0x39e, "ICDBTRL", 0x00000000, 0x00000000},
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{0x39f, "ICDBTRH", 0x00000000, 0x00000000},
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{0x3b2, "MMUCR", 0x00000000, 0x00000000},
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{0x3b3, "CCR0", 0x00000000, 0x00000000},
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{0x3d3, "ICDBDR", 0x00000000, 0x00000000},
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{0x3f3, "DBDR", 0x00000000, 0x00000000},
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};
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static int spr_test_list_size = ARRAY_SIZE(spr_test_list);
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int spr_post_test (int flags)
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{
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int ret = 0;
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int i;
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unsigned long code[] = {
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0x7c6002a6, /* mfspr r3,SPR */
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0x4e800020 /* blr */
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};
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unsigned long (*get_spr) (void) = (void *) code;
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#ifdef CONFIG_4xx_DCACHE
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/* disable cache */
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change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
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#endif
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for (i = 0; i < spr_test_list_size; i++) {
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int num = spr_test_list[i].number;
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/* mfspr r3,num */
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code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
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asm volatile ("isync");
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if ((get_spr () & spr_test_list[i].mask) !=
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(spr_test_list[i].value & spr_test_list[i].mask)) {
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post_log ("The value of %s special register "
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"is incorrect: 0x%08X\n",
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spr_test_list[i].name, get_spr ());
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ret = -1;
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}
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}
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#ifdef CONFIG_4xx_DCACHE
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/* enable cache */
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change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
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#endif
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return ret;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */
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