u-boot/arch/riscv/cpu/ax25/Kconfig at 60262cd041529cabd5fbabb6f2077495fa922fca - Mirrors/u-boot - CherryKitten

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Rick Chen 52923c6db7 riscv: cache: Implement i/dcache [status, enable, disable]

AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.

This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.

This approach also provide the expansion when the
vender specific features are going to join in.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>

2018-11-26 13:58:01 +08:00

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 config RISCV_NDS
 	bool "AndeStar V5 ISA support"
 	default n
 	help
 		Say Y here if you plan to run U-Boot on AndeStar v5
 		platforms and use some specific features which are
 		provided by Andes Technology AndeStar V5 Families.