u-boot/arch/arm/dts/ls1021a-tsn.dts

// SPDX-License-Identifier: GPL-2.0
/* Copyright 2016-2018 NXP
 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
 */

/dts-v1/;
#include "ls1021a.dtsi"

/ {
	model = "NXP LS1021A-TSN Board";

	aliases {
		enet0-sgmii-phy = &sgmii_phy2;
		enet1-sgmii-phy = &sgmii_phy1;
		spi0 = &qspi;
		spi1 = &dspi1;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &swp2;
		ethernet4 = &swp3;
		ethernet5 = &swp4;
		ethernet6 = &swp5;
	};
};

&dspi0 {
	bus-num = <0>;
	status = "okay";

	sja1105: ethernet-switch@1 {
		reg = <0x1>;
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nxp,sja1105t";
		/* 12 MHz */
		spi-max-frequency = <12000000>;
		/* Sample data on trailing clock edge */
		spi-cpha;
		/* SPI controller settings for SJA1105 timing requirements */
		fsl,spi-cs-sck-delay = <1000>;
		fsl,spi-sck-cs-delay = <1000>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			swp5: port@0 {
				/* ETH5 written on chassis */
				label = "swp5";
				phy-handle = <&rgmii_phy6>;
				phy-mode = "rgmii-id";
				reg = <0>;
			};

			swp2: port@1 {
				/* ETH2 written on chassis */
				label = "swp2";
				phy-handle = <&rgmii_phy3>;
				phy-mode = "rgmii-id";
				reg = <1>;
			};

			swp3: port@2 {
				/* ETH3 written on chassis */
				label = "swp3";
				phy-handle = <&rgmii_phy4>;
				phy-mode = "rgmii-id";
				reg = <2>;
			};

			swp4: port@3 {
				/* ETH4 written on chassis */
				label = "swp4";
				phy-handle = <&rgmii_phy5>;
				phy-mode = "rgmii-id";
				reg = <3>;
			};

			port@4 {
				/* Internal port connected to eth2 */
				ethernet = <&enet2>;
				phy-mode = "rgmii";
				reg = <4>;

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
		};
	};
};

&enet0 {
	tbi-handle = <&tbi0>;
	phy-handle = <&sgmii_phy2>;
	phy-mode = "sgmii";
	status = "okay";
};

&enet1 {
	tbi-handle = <&tbi1>;
	phy-handle = <&sgmii_phy1>;
	phy-mode = "sgmii";
	status = "okay";
};

/* RGMII delays added via PCB traces */
&enet2 {
	phy-mode = "rgmii";
	status = "okay";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&i2c0 {
	status = "okay";
};

&mdio0 {
	/* AR8031 */
	sgmii_phy1: ethernet-phy@1 {
		reg = <0x1>;
	};

	/* AR8031 */
	sgmii_phy2: ethernet-phy@2 {
		reg = <0x2>;
	};

	/* BCM5464 quad PHY */
	rgmii_phy3: ethernet-phy@3 {
		reg = <0x3>;
	};

	rgmii_phy4: ethernet-phy@4 {
		reg = <0x4>;
	};

	rgmii_phy5: ethernet-phy@5 {
		reg = <0x5>;
	};

	rgmii_phy6: ethernet-phy@6 {
		reg = <0x6>;
	};

	/* SGMII PCS for enet0 */
	tbi0: tbi-phy@1f {
		reg = <0x1f>;
		device_type = "tbi-phy";
	};
};

&mdio1 {
	/* SGMII PCS for enet1 */
	tbi1: tbi-phy@1f {
		reg = <0x1f>;
		device_type = "tbi-phy";
	};
};

&qspi {
	bus-num = <0>;
	status = "okay";

	flash@0 {
		compatible = "spi-flash";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&uart0 {
	status = "okay";
};