mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-29 19:02:12 +00:00
69ef98b209
Device tree alignment with Linux kernel v5.19-rc1 - ARM: dts: stm32: Add alternate pinmux for ethernet0 pins - ARM: dts: stm32: Add alternate pinmux for mco2 pins - ARM: dts: stm32: fix pinctrl node name warnings (MPU soc) - ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group - dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 - dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15 - dt-bindings: clock: stm32mp15: rename CK_SCMI define - dt-bindings: reset: stm32mp15: rename RST_SCMI define - dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 - dt-bindings: clk: cleanup comments - ARM: dts: align SPI NOR node name with dtschema - ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15 - ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 + patch from stm32-dt-for-v5.19-fixes-2 - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 - ARM: dts: stm32: fix pwr regulators references to use scmi - ARM: dts: stm32: use the correct clock source for CEC on stm32mp151 - ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board - ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI - ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
109 lines
2 KiB
Text
109 lines
2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
/*
|
|
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
|
*/
|
|
|
|
/ {
|
|
firmware {
|
|
optee: optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
};
|
|
|
|
scmi: scmi {
|
|
compatible = "linaro,scmi-optee";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
linaro,optee-channel-id = <0>;
|
|
shmem = <&scmi_shm>;
|
|
|
|
scmi_clk: protocol@14 {
|
|
reg = <0x14>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
scmi_reset: protocol@16 {
|
|
reg = <0x16>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
scmi_voltd: protocol@17 {
|
|
reg = <0x17>;
|
|
|
|
scmi_reguls: regulators {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
scmi_reg11: reg11@0 {
|
|
reg = <0>;
|
|
regulator-name = "reg11";
|
|
regulator-min-microvolt = <1100000>;
|
|
regulator-max-microvolt = <1100000>;
|
|
};
|
|
|
|
scmi_reg18: reg18@1 {
|
|
voltd-name = "reg18";
|
|
reg = <1>;
|
|
regulator-name = "reg18";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
scmi_usb33: usb33@2 {
|
|
reg = <2>;
|
|
regulator-name = "usb33";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
soc {
|
|
scmi_sram: sram@2ffff000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x2ffff000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x2ffff000 0x1000>;
|
|
|
|
scmi_shm: scmi-sram@0 {
|
|
compatible = "arm,scmi-shmem";
|
|
reg = <0 0x80>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
®11 {
|
|
status = "disabled";
|
|
};
|
|
|
|
®18 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&usb33 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&usbotg_hs {
|
|
usb33d-supply = <&scmi_usb33>;
|
|
};
|
|
|
|
&usbphyc {
|
|
vdda1v1-supply = <&scmi_reg11>;
|
|
vdda1v8-supply = <&scmi_reg18>;
|
|
};
|
|
|
|
/delete-node/ &clk_hse;
|
|
/delete-node/ &clk_hsi;
|
|
/delete-node/ &clk_lse;
|
|
/delete-node/ &clk_lsi;
|
|
/delete-node/ &clk_csi;
|
|
/delete-node/ ®11;
|
|
/delete-node/ ®18;
|
|
/delete-node/ &usb33;
|
|
/delete-node/ &pwr_regulators;
|