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https://github.com/AsahiLinux/u-boot
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1b2f4697c0
Introduce the basic AM62 SoC description dtsi files describing most peripherals as per kernel dts. Signed-off-by: Gowtham Tammana <g-tammana@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
105 lines
3.7 KiB
Text
105 lines
3.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM62 SoC Family
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*
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* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/k3.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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/ {
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model = "Texas Instruments K3 AM625 SoC";
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compatible = "ti,am625";
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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a53_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: bus@f0000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
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<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
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<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
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<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
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<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
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<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
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<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
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<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
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<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
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<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
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<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
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<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
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<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
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<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
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<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
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<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
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<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
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<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
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<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
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<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
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<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
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<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
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/* MCU Domain Range */
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<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
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/* Wakeup Domain Range */
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<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
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<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
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cbass_mcu: bus@4000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
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};
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cbass_wakeup: bus@2b000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
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<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
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};
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};
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};
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/* Now include the peripherals for each bus segments */
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#include "k3-am62-main.dtsi"
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#include "k3-am62-mcu.dtsi"
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#include "k3-am62-wakeup.dtsi"
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