mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
a06752e36b
- Added I2C support for ML300.
- Added support for ML300 to read out its environment information
stored on the EEPROM.
- Added support to use board specific parameters as part of
U-Boot's environment information.
- Updated MLD files to support configuration for new features
above.
* Patches by Travis Sawyer, 5 Aug 2004:
- Remove incorrect bridge settings for eth group 6
- Add call to setup bridge in ppc_440x_eth_initialize
- Fix ppc_440x_eth_init to reset the phy only if its the
first time through, otherwise, just check the phy for the
autonegotiated speed/duplex. This allows the use of netconsole
- only print the speed/duplex the first time the phy is reset.
150 lines
6 KiB
C
150 lines
6 KiB
C
/* $Id: xiic_l.h,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
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/*****************************************************************************
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
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* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
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* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
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* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE.
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*
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* (c) Copyright 2002 Xilinx Inc.
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* All rights reserved.
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*
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*****************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file xiic_l.h
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*
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* This header file contains identifiers and low-level driver functions (or
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* macros) that can be used to access the device. High-level driver functions
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* are defined in xiic.h.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00b jhl 05/07/02 First release
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* 1.01c ecm 12/05/02 new rev
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* </pre>
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*
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*****************************************************************************/
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#ifndef XIIC_L_H /* prevent circular inclusions */
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#define XIIC_L_H /* by using protection macros */
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/***************************** Include Files ********************************/
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#include "xbasic_types.h"
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/************************** Constant Definitions ****************************/
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#define XIIC_MSB_OFFSET 3
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#define XIIC_REG_OFFSET 0x100 + XIIC_MSB_OFFSET
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/*
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* Register offsets in bytes from RegisterBase. Three is added to the
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* base offset to access LSB (IBM style) of the word
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*/
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#define XIIC_CR_REG_OFFSET 0x00+XIIC_REG_OFFSET /* Control Register */
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#define XIIC_SR_REG_OFFSET 0x04+XIIC_REG_OFFSET /* Status Register */
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#define XIIC_DTR_REG_OFFSET 0x08+XIIC_REG_OFFSET /* Data Tx Register */
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#define XIIC_DRR_REG_OFFSET 0x0C+XIIC_REG_OFFSET /* Data Rx Register */
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#define XIIC_ADR_REG_OFFSET 0x10+XIIC_REG_OFFSET /* Address Register */
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#define XIIC_TFO_REG_OFFSET 0x14+XIIC_REG_OFFSET /* Tx FIFO Occupancy */
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#define XIIC_RFO_REG_OFFSET 0x18+XIIC_REG_OFFSET /* Rx FIFO Occupancy */
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#define XIIC_TBA_REG_OFFSET 0x1C+XIIC_REG_OFFSET /* 10 Bit Address reg */
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#define XIIC_RFD_REG_OFFSET 0x20+XIIC_REG_OFFSET /* Rx FIFO Depth reg */
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/* Control Register masks */
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#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
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#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
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#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
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#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
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#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
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#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
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#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
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/* Status Register masks */
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#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
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#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
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#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
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#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
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#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
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#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
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#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
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/* IPIF Interrupt Status Register masks Interrupt occurs when... */
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#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
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#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete*/
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#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
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#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level*/
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#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
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#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
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#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
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#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
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/* IPIF Device Interrupt Register masks */
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#define XIIC_IPIF_IIC_MASK 0x00000004UL /* 1=inter enabled */
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#define XIIC_IPIF_ERROR_MASK 0x00000001UL /* 1=inter enabled */
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#define XIIC_IPIF_INTER_ENABLE_MASK (XIIC_IPIF_IIC_MASK | \
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XIIC_IPIF_ERROR_MASK)
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#define XIIC_TX_ADDR_SENT 0x00
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#define XIIC_TX_ADDR_MSTR_RECV_MASK 0x02
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/* The following constants specify the depth of the FIFOs */
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#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
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#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
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/* The following constants specify groups of interrupts that are typically
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* enabled or disables at the same time
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*/
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#define XIIC_TX_INTERRUPTS \
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(XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | \
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XIIC_INTR_TX_HALF_MASK)
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#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
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/* The following constants are used with the following macros to specify the
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* operation, a read or write operation.
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*/
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#define XIIC_READ_OPERATION 1
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#define XIIC_WRITE_OPERATION 0
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/* The following constants are used with the transmit FIFO fill function to
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* specify the role which the IIC device is acting as, a master or a slave.
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*/
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#define XIIC_MASTER_ROLE 1
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#define XIIC_SLAVE_ROLE 0
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/**************************** Type Definitions ******************************/
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/***************** Macros (Inline Functions) Definitions ********************/
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/************************** Function Prototypes *****************************/
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unsigned XIic_Recv(u32 BaseAddress, u8 Address,
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u8 *BufferPtr, unsigned ByteCount);
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unsigned XIic_Send(u32 BaseAddress, u8 Address,
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u8 *BufferPtr, unsigned ByteCount);
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#endif /* end of protection macro */
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