mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-27 15:12:21 +00:00
a09fea1d28
- In ARMv8 NXP Layerscape platforms we also need to make use of CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so. - On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define to 0. - Add Kconfig entry for ENV_ADDR. - Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it. - Add ENV_xxx_REDUND options that depend on their primary option and SYS_REDUNDAND_ENVIRONMENT - On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR for the pre-main-U-Boot environment location. - On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but rather it being non-zero, as it will now be zero by default. - Rework the env_offset absolute in env/embedded.o to not use CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within ENV_IS_IN_FLASH. - Migrate all platforms. Cc: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
440 lines
13 KiB
C
440 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2006-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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/*
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* mpc8349emds board configuration file
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00100000
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/*
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* DDR Setup
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*/
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#define CONFIG_DDR_ECC /* support DDR ECC function */
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#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
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#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
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/*
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* SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
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* unselect it to use old spd_sdram.c
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*/
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define SPD_EEPROM_ADDRESS1 0x52
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#define SPD_EEPROM_ADDRESS2 0x51
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#define CONFIG_DIMM_SLOTS_PER_CTLR 2
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#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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/*
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* 32-bit data path mode.
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*
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* Please note that using this mode for devices with the real density of 64-bit
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* effectively reduces the amount of available memory due to the effect of
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* wrapping around while translating address to row/columns, for example in the
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* 256MB module the upper 128MB get aliased with contents of the lower
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* 128MB); normally this define should be used for devices with real 32-bit
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* data path.
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*/
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#undef CONFIG_DDR_32BIT
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
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| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#undef CONFIG_DDR_2T_TIMING
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/*
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* DDRCDR - DDR Control Driver Register
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*/
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#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
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#if defined(CONFIG_SPD_EEPROM)
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/*
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* Determine DDR configuration from I2C interface.
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*/
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
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#else
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/*
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* Manually set up DDR parameters
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*/
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#define CONFIG_SYS_DDR_SIZE 256 /* MB */
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#if defined(CONFIG_DDR_II)
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#define CONFIG_SYS_DDRCDR 0x80080001
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#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
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#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
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#define CONFIG_SYS_DDR_TIMING_0 0x00220802
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#define CONFIG_SYS_DDR_TIMING_1 0x38357322
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#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
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#define CONFIG_SYS_DDR_MODE 0x47d00432
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#define CONFIG_SYS_DDR_MODE2 0x8000c000
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#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
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#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#else
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#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_10)
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#define CONFIG_SYS_DDR_TIMING_1 0x36332321
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#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
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#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
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#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
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#if defined(CONFIG_DDR_32BIT)
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/* set burst length to 8 for 32-bit data path */
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/* DLL,normal,seq,4/2.5, 8 burst len */
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#define CONFIG_SYS_DDR_MODE 0x00000023
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#else
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/* the default burst length is 4 - for 64-bit data path */
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/* DLL,normal,seq,4/2.5, 4 burst len */
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#define CONFIG_SYS_DDR_MODE 0x00000022
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#endif
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#endif
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#endif
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/*
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* SDRAM on the Local Bus
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*/
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#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
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#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
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#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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/*
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* BCSR register on local bus 32KB, 8-bit wide for MDS config reg
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*/
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#define CONFIG_SYS_BCSR 0xE2400000
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/* Access window base at BCSR base */
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
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/*
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* The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
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*/
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/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
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/*
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* Base Register 2 and Option Register 2 configure SDRAM.
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* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
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*
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* For BR2, need:
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* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
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* port-size = 32-bits = BR2[19:20] = 11
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* no parity checking = BR2[21:22] = 00
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* SDRAM for MSEL = BR2[24:26] = 011
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* Valid = BR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
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*/
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/*
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* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
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*
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* For OR2, need:
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* 64MB mask for AM, OR2[0:7] = 1111 1100
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* XAM, OR2[17:18] = 11
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* 9 columns OR2[19-21] = 010
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* 13 rows OR2[23-25] = 100
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* EAD set for extra time OR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
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*/
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/* LB sdram refresh timer, about 6us */
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#define CONFIG_SYS_LBC_LSRT 0x32000000
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/* LB refresh timer prescal, 266MHz/32 */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
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| LSDMR_BSMA1516 \
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| LSDMR_RFCR8 \
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| LSDMR_PRETOACT6 \
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| LSDMR_ACTTORW3 \
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| LSDMR_BL8 \
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| LSDMR_WRC3 \
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| LSDMR_CL3)
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/*
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* SDRAM Controller configuration sequence.
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*/
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#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
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#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
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#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
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#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
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#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
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/* SPI */
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#undef CONFIG_SOFT_SPI /* SPI bit-banged */
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/* GPIOs. Used as SPI chip selects */
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#define CONFIG_SYS_GPIO1_PRELIM
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#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
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#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
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/* TSEC */
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
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/* USB */
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#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
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#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
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#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
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#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
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#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
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#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
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#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
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#if defined(CONFIG_PCI)
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#define CONFIG_83XX_PCI_STREAMING
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#if !defined(CONFIG_PCI_PNP)
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#define PCI_ENET0_IOADDR 0xFIXME
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#define PCI_ENET0_MEMADDR 0xFIXME
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#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
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#endif
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#endif /* CONFIG_PCI */
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/*
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* TSEC configuration
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*/
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_GMII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC0"
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Configure on-board RTC
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*/
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#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/*
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* Environment
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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/* Address and size of Redundant Environment Sector */
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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/* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
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/*
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* System performance
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*/
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#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
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#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
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#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
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#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
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/* System IO Config */
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#define CONFIG_SYS_SICRH 0
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#define CONFIG_SYS_SICRL SICRL_LDP_A
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
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#endif
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/*
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* Environment Configuration
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*/
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH0
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#endif
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#define CONFIG_HOSTNAME "mpc8349emds"
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#define CONFIG_ROOTPATH "/nfsroot/rootfs"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"hostname=mpc8349emds\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
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"update=protect off fe000000 fe03ffff; " \
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"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
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"upd=run load update\0" \
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"fdtaddr=780000\0" \
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"fdtfile=mpc834x_mds.dtb\0" \
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""
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
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"$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#endif /* __CONFIG_H */
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