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https://github.com/AsahiLinux/u-boot
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910f1ae3eb
Two new options: CONFIG_PL011_SERIAL_RLCR Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500) have separate receive and transmit line control registers. Set this variable to initialize the extra register. CONFIG_PL011_SERIAL_FLUSH_ON_INIT On some platforms (e.g. U8500) U-Boot is loaded by a second stage boot loader that has already initialized the UART. Define this variable to flush the UART at init time. empty fifo on init Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
144 lines
5.3 KiB
C
144 lines
5.3 KiB
C
/*
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* (C) Copyright 2003, 2004
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* ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* ARM PrimeCell UART's (PL010 & PL011)
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* ------------------------------------
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*
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* Definitions common to both PL010 & PL011
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*
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*/
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#ifndef __ASSEMBLY__
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/*
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* We can use a combined structure for PL010 and PL011, because they overlap
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* only in common registers.
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*/
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struct pl01x_regs {
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u32 dr; /* 0x00 Data register */
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u32 ecr; /* 0x04 Error clear register (Write) */
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u32 pl010_lcrh; /* 0x08 Line control register, high byte */
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u32 pl010_lcrm; /* 0x0C Line control register, middle byte */
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u32 pl010_lcrl; /* 0x10 Line control register, low byte */
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u32 pl010_cr; /* 0x14 Control register */
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u32 fr; /* 0x18 Flag register (Read only) */
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#ifdef CONFIG_PL011_SERIAL_RLCR
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u32 pl011_rlcr; /* 0x1c Receive line control register */
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#else
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u32 reserved;
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#endif
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u32 ilpr; /* 0x20 IrDA low-power counter register */
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u32 pl011_ibrd; /* 0x24 Integer baud rate register */
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u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
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u32 pl011_lcrh; /* 0x2C Line control register */
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u32 pl011_cr; /* 0x30 Control register */
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};
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#endif
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#define UART_PL01x_RSR_OE 0x08
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#define UART_PL01x_RSR_BE 0x04
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#define UART_PL01x_RSR_PE 0x02
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#define UART_PL01x_RSR_FE 0x01
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#define UART_PL01x_FR_TXFE 0x80
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#define UART_PL01x_FR_RXFF 0x40
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#define UART_PL01x_FR_TXFF 0x20
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#define UART_PL01x_FR_RXFE 0x10
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#define UART_PL01x_FR_BUSY 0x08
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#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
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/*
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* PL010 definitions
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*
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*/
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#define UART_PL010_CR_LPE (1 << 7)
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#define UART_PL010_CR_RTIE (1 << 6)
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#define UART_PL010_CR_TIE (1 << 5)
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#define UART_PL010_CR_RIE (1 << 4)
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#define UART_PL010_CR_MSIE (1 << 3)
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#define UART_PL010_CR_IIRLP (1 << 2)
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#define UART_PL010_CR_SIREN (1 << 1)
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#define UART_PL010_CR_UARTEN (1 << 0)
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#define UART_PL010_LCRH_WLEN_8 (3 << 5)
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#define UART_PL010_LCRH_WLEN_7 (2 << 5)
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#define UART_PL010_LCRH_WLEN_6 (1 << 5)
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#define UART_PL010_LCRH_WLEN_5 (0 << 5)
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#define UART_PL010_LCRH_FEN (1 << 4)
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#define UART_PL010_LCRH_STP2 (1 << 3)
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#define UART_PL010_LCRH_EPS (1 << 2)
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#define UART_PL010_LCRH_PEN (1 << 1)
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#define UART_PL010_LCRH_BRK (1 << 0)
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#define UART_PL010_BAUD_460800 1
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#define UART_PL010_BAUD_230400 3
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#define UART_PL010_BAUD_115200 7
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#define UART_PL010_BAUD_57600 15
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#define UART_PL010_BAUD_38400 23
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#define UART_PL010_BAUD_19200 47
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#define UART_PL010_BAUD_14400 63
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#define UART_PL010_BAUD_9600 95
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#define UART_PL010_BAUD_4800 191
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#define UART_PL010_BAUD_2400 383
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#define UART_PL010_BAUD_1200 767
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/*
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* PL011 definitions
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*
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*/
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#define UART_PL011_LCRH_SPS (1 << 7)
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#define UART_PL011_LCRH_WLEN_8 (3 << 5)
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#define UART_PL011_LCRH_WLEN_7 (2 << 5)
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#define UART_PL011_LCRH_WLEN_6 (1 << 5)
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#define UART_PL011_LCRH_WLEN_5 (0 << 5)
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#define UART_PL011_LCRH_FEN (1 << 4)
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#define UART_PL011_LCRH_STP2 (1 << 3)
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#define UART_PL011_LCRH_EPS (1 << 2)
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#define UART_PL011_LCRH_PEN (1 << 1)
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#define UART_PL011_LCRH_BRK (1 << 0)
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#define UART_PL011_CR_CTSEN (1 << 15)
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#define UART_PL011_CR_RTSEN (1 << 14)
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#define UART_PL011_CR_OUT2 (1 << 13)
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#define UART_PL011_CR_OUT1 (1 << 12)
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#define UART_PL011_CR_RTS (1 << 11)
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#define UART_PL011_CR_DTR (1 << 10)
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#define UART_PL011_CR_RXE (1 << 9)
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#define UART_PL011_CR_TXE (1 << 8)
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#define UART_PL011_CR_LPE (1 << 7)
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#define UART_PL011_CR_IIRLP (1 << 2)
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#define UART_PL011_CR_SIREN (1 << 1)
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#define UART_PL011_CR_UARTEN (1 << 0)
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#define UART_PL011_IMSC_OEIM (1 << 10)
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#define UART_PL011_IMSC_BEIM (1 << 9)
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#define UART_PL011_IMSC_PEIM (1 << 8)
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#define UART_PL011_IMSC_FEIM (1 << 7)
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#define UART_PL011_IMSC_RTIM (1 << 6)
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#define UART_PL011_IMSC_TXIM (1 << 5)
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#define UART_PL011_IMSC_RXIM (1 << 4)
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#define UART_PL011_IMSC_DSRMIM (1 << 3)
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#define UART_PL011_IMSC_DCDMIM (1 << 2)
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#define UART_PL011_IMSC_CTSMIM (1 << 1)
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#define UART_PL011_IMSC_RIMIM (1 << 0)
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