Praveen Rao 5f603761c3 ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870 ... This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>		2015-03-13 09:29:01 -04:00
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asm	ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870	2015-03-13 09:29:01 -04:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00