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5f24d0cb9c
Introduce clk implementation for i.MX8MM, including pll configuration, ccm configuration. Mostly will be done clk dm driver, but such as DRAM part, we still use non clk dm driver, because we have limited sram. Signed-off-by: Peng Fan <peng.fan@nxp.com>
387 lines
9 KiB
C
387 lines
9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018-2019 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*/
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#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
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#define _ASM_ARCH_IMX8MM_CLOCK_H
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#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
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{ \
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.rate = (_rate), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.kdiv = (_k), \
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}
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#define LOCK_STATUS BIT(31)
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#define LOCK_SEL_MASK BIT(29)
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#define CLKE_MASK BIT(11)
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#define RST_MASK BIT(9)
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#define BYPASS_MASK BIT(4)
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#define MDIV_SHIFT 12
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#define MDIV_MASK GENMASK(21, 12)
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#define PDIV_SHIFT 4
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#define PDIV_MASK GENMASK(9, 4)
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#define SDIV_SHIFT 0
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#define SDIV_MASK GENMASK(2, 0)
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#define KDIV_SHIFT 0
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#define KDIV_MASK GENMASK(15, 0)
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struct imx_int_pll_rate_table {
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u32 rate;
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int mdiv;
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int pdiv;
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int sdiv;
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int kdiv;
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};
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enum pll_clocks {
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ANATOP_ARM_PLL,
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ANATOP_VPU_PLL,
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ANATOP_GPU_PLL,
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ANATOP_SYSTEM_PLL1,
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ANATOP_SYSTEM_PLL2,
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ANATOP_SYSTEM_PLL3,
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ANATOP_AUDIO_PLL1,
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ANATOP_AUDIO_PLL2,
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ANATOP_VIDEO_PLL,
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ANATOP_DRAM_PLL,
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};
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enum clk_root_index {
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ARM_A53_CLK_ROOT = 0,
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ARM_M4_CLK_ROOT = 1,
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VPU_A53_CLK_ROOT = 2,
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GPU3D_CLK_ROOT = 3,
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GPU2D_CLK_ROOT = 4,
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MAIN_AXI_CLK_ROOT = 16,
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ENET_AXI_CLK_ROOT = 17,
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NAND_USDHC_BUS_CLK_ROOT = 18,
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VPU_BUS_CLK_ROOT = 19,
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DISPLAY_AXI_CLK_ROOT = 20,
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DISPLAY_APB_CLK_ROOT = 21,
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DISPLAY_RTRM_CLK_ROOT = 22,
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USB_BUS_CLK_ROOT = 23,
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GPU_AXI_CLK_ROOT = 24,
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GPU_AHB_CLK_ROOT = 25,
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NOC_CLK_ROOT = 26,
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NOC_APB_CLK_ROOT = 27,
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AHB_CLK_ROOT = 32,
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IPG_CLK_ROOT = 33,
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AUDIO_AHB_CLK_ROOT = 34,
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MIPI_DSI_ESC_RX_CLK_ROOT = 36,
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DRAM_SEL_CFG = 48,
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CORE_SEL_CFG = 49,
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DRAM_ALT_CLK_ROOT = 64,
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DRAM_APB_CLK_ROOT = 65,
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VPU_G1_CLK_ROOT = 66,
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VPU_G2_CLK_ROOT = 67,
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DISPLAY_DTRC_CLK_ROOT = 68,
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DISPLAY_DC8000_CLK_ROOT = 69,
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PCIE_CTRL_CLK_ROOT = 70,
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PCIE_PHY_CLK_ROOT = 71,
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PCIE_AUX_CLK_ROOT = 72,
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DC_PIXEL_CLK_ROOT = 73,
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LCDIF_PIXEL_CLK_ROOT = 74,
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SAI1_CLK_ROOT = 75,
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SAI2_CLK_ROOT = 76,
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SAI3_CLK_ROOT = 77,
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SAI4_CLK_ROOT = 78,
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SAI5_CLK_ROOT = 79,
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SAI6_CLK_ROOT = 80,
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SPDIF1_CLK_ROOT = 81,
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SPDIF2_CLK_ROOT = 82,
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ENET_REF_CLK_ROOT = 83,
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ENET_TIMER_CLK_ROOT = 84,
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ENET_PHY_REF_CLK_ROOT = 85,
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NAND_CLK_ROOT = 86,
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QSPI_CLK_ROOT = 87,
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USDHC1_CLK_ROOT = 88,
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USDHC2_CLK_ROOT = 89,
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I2C1_CLK_ROOT = 90,
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I2C2_CLK_ROOT = 91,
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I2C3_CLK_ROOT = 92,
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I2C4_CLK_ROOT = 93,
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UART1_CLK_ROOT = 94,
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UART2_CLK_ROOT = 95,
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UART3_CLK_ROOT = 96,
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UART4_CLK_ROOT = 97,
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USB_CORE_REF_CLK_ROOT = 98,
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USB_PHY_REF_CLK_ROOT = 99,
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GIC_CLK_ROOT = 100,
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ECSPI1_CLK_ROOT = 101,
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ECSPI2_CLK_ROOT = 102,
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PWM1_CLK_ROOT = 103,
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PWM2_CLK_ROOT = 104,
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PWM3_CLK_ROOT = 105,
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PWM4_CLK_ROOT = 106,
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GPT1_CLK_ROOT = 107,
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GPT2_CLK_ROOT = 108,
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GPT3_CLK_ROOT = 109,
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GPT4_CLK_ROOT = 110,
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GPT5_CLK_ROOT = 111,
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GPT6_CLK_ROOT = 112,
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TRACE_CLK_ROOT = 113,
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WDOG_CLK_ROOT = 114,
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WRCLK_CLK_ROOT = 115,
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IPP_DO_CLKO1 = 116,
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IPP_DO_CLKO2 = 117,
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MIPI_DSI_CORE_CLK_ROOT = 118,
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MIPI_DSI_PHY_REF_CLK_ROOT = 119,
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MIPI_DSI_DBI_CLK_ROOT = 120,
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USDHC3_CLK_ROOT = 121,
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MIPI_CSI1_CORE_CLK_ROOT = 122,
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MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
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MIPI_CSI1_ESC_CLK_ROOT = 124,
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MIPI_CSI2_CORE_CLK_ROOT = 125,
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MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
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MIPI_CSI2_ESC_CLK_ROOT = 127,
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PCIE2_CTRL_CLK_ROOT = 128,
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PCIE2_PHY_CLK_ROOT = 129,
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PCIE2_AUX_CLK_ROOT = 130,
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ECSPI3_CLK_ROOT = 131,
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PDM_CLK_ROOT = 132,
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VPU_H1_CLK_ROOT = 133,
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CLK_ROOT_MAX,
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};
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enum clk_root_src {
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OSC_24M_CLK,
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ARM_PLL_CLK,
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DRAM_PLL1_CLK,
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VIDEO_PLL2_CLK,
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VPU_PLL_CLK,
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GPU_PLL_CLK,
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SYSTEM_PLL1_800M_CLK,
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SYSTEM_PLL1_400M_CLK,
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SYSTEM_PLL1_266M_CLK,
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SYSTEM_PLL1_200M_CLK,
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SYSTEM_PLL1_160M_CLK,
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SYSTEM_PLL1_133M_CLK,
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SYSTEM_PLL1_100M_CLK,
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SYSTEM_PLL1_80M_CLK,
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SYSTEM_PLL1_40M_CLK,
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SYSTEM_PLL2_1000M_CLK,
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SYSTEM_PLL2_500M_CLK,
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SYSTEM_PLL2_333M_CLK,
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SYSTEM_PLL2_250M_CLK,
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SYSTEM_PLL2_200M_CLK,
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SYSTEM_PLL2_166M_CLK,
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SYSTEM_PLL2_125M_CLK,
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SYSTEM_PLL2_100M_CLK,
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SYSTEM_PLL2_50M_CLK,
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SYSTEM_PLL3_CLK,
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AUDIO_PLL1_CLK,
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AUDIO_PLL2_CLK,
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VIDEO_PLL_CLK,
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OSC_32K_CLK,
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EXT_CLK_1,
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EXT_CLK_2,
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EXT_CLK_3,
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EXT_CLK_4,
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OSC_HDMI_CLK
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};
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enum clk_ccgr_index {
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CCGR_DVFS = 0,
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CCGR_ANAMIX = 1,
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CCGR_CPU = 2,
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CCGR_CSU = 3,
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CCGR_DEBUG = 4,
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CCGR_DDR1 = 5,
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CCGR_ECSPI1 = 7,
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CCGR_ECSPI2 = 8,
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CCGR_ECSPI3 = 9,
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CCGR_ENET1 = 10,
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CCGR_GPIO1 = 11,
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CCGR_GPIO2 = 12,
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CCGR_GPIO3 = 13,
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CCGR_GPIO4 = 14,
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CCGR_GPIO5 = 15,
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CCGR_GPT1 = 16,
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CCGR_GPT2 = 17,
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CCGR_GPT3 = 18,
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CCGR_GPT4 = 19,
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CCGR_GPT5 = 20,
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CCGR_GPT6 = 21,
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CCGR_HS = 22,
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CCGR_I2C1 = 23,
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CCGR_I2C2 = 24,
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CCGR_I2C3 = 25,
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CCGR_I2C4 = 26,
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CCGR_IOMUX = 27,
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CCGR_IOMUX1 = 28,
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CCGR_IOMUX2 = 29,
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CCGR_IOMUX3 = 30,
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CCGR_IOMUX4 = 31,
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CCGR_SNVSMIX_IPG_CLK = 32,
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CCGR_MU = 33,
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CCGR_OCOTP = 34,
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CCGR_OCRAM = 35,
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CCGR_OCRAM_S = 36,
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CCGR_PCIE = 37,
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CCGR_PERFMON1 = 38,
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CCGR_PERFMON2 = 39,
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CCGR_PWM1 = 40,
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CCGR_PWM2 = 41,
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CCGR_PWM3 = 42,
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CCGR_PWM4 = 43,
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CCGR_QOS = 44,
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CCGR_QOS_DISPMIX = 45,
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CCGR_QOS_ETHENET = 46,
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CCGR_QSPI = 47,
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CCGR_RAWNAND = 48,
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CCGR_RDC = 49,
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CCGR_ROM = 50,
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CCGR_SAI1 = 51,
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CCGR_SAI2 = 52,
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CCGR_SAI3 = 53,
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CCGR_SAI4 = 54,
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CCGR_SAI5 = 55,
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CCGR_SAI6 = 56,
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CCGR_SCTR = 57,
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CCGR_SDMA1 = 58,
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CCGR_SDMA2 = 59,
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CCGR_SEC_DEBUG = 60,
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CCGR_SEMA1 = 61,
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CCGR_SEMA2 = 62,
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CCGR_SIM_DISPLAY = 63,
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CCGR_SIM_ENET = 64,
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CCGR_SIM_M = 65,
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CCGR_SIM_MAIN = 66,
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CCGR_SIM_S = 67,
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CCGR_SIM_WAKEUP = 68,
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CCGR_SIM_HSIO = 69,
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CCGR_SIM_VPU = 70,
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CCGR_SNVS = 71,
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CCGR_TRACE = 72,
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CCGR_UART1 = 73,
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CCGR_UART2 = 74,
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CCGR_UART3 = 75,
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CCGR_UART4 = 76,
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CCGR_USB_MSCALE_PL301 = 77,
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CCGR_GPU3D = 79,
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CCGR_USDHC1 = 81,
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CCGR_USDHC2 = 82,
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CCGR_WDOG1 = 83,
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CCGR_WDOG2 = 84,
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CCGR_WDOG3 = 85,
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CCGR_VPUG1 = 86,
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CCGR_GPU_BUS = 87,
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CCGR_VPUH1 = 89,
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CCGR_VPUG2 = 90,
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CCGR_PDM = 91,
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CCGR_GIC = 92,
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CCGR_DISPMIX = 93,
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CCGR_USDHC3 = 94,
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CCGR_SDMA3 = 95,
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CCGR_XTAL = 96,
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CCGR_PLL = 97,
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CCGR_TEMP_SENSOR = 98,
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CCGR_VPUMIX_BUS = 99,
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CCGR_GPU2D = 102,
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CCGR_MAX
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};
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enum clk_src_index {
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CLK_SRC_CKIL_SYNC_REQ = 0,
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CLK_SRC_ARM_PLL_EN = 1,
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CLK_SRC_GPU_PLL_EN = 2,
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CLK_SRC_VPU_PLL_EN = 3,
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CLK_SRC_DRAM_PLL_EN = 4,
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CLK_SRC_SYSTEM_PLL1_EN = 5,
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CLK_SRC_SYSTEM_PLL2_EN = 6,
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CLK_SRC_SYSTEM_PLL3_EN = 7,
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CLK_SRC_AUDIO_PLL1_EN = 8,
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CLK_SRC_AUDIO_PLL2_EN = 9,
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CLK_SRC_VIDEO_PLL1_EN = 10,
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CLK_SRC_RESERVED = 11,
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CLK_SRC_ARM_PLL = 12,
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CLK_SRC_GPU_PLL = 13,
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CLK_SRC_VPU_PLL = 14,
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CLK_SRC_DRAM_PLL = 15,
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CLK_SRC_SYSTEM_PLL1_800M = 16,
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CLK_SRC_SYSTEM_PLL1_400M = 17,
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CLK_SRC_SYSTEM_PLL1_266M = 18,
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CLK_SRC_SYSTEM_PLL1_200M = 19,
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CLK_SRC_SYSTEM_PLL1_160M = 20,
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CLK_SRC_SYSTEM_PLL1_133M = 21,
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CLK_SRC_SYSTEM_PLL1_100M = 22,
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CLK_SRC_SYSTEM_PLL1_80M = 23,
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CLK_SRC_SYSTEM_PLL1_40M = 24,
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CLK_SRC_SYSTEM_PLL2_1000M = 25,
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CLK_SRC_SYSTEM_PLL2_500M = 26,
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CLK_SRC_SYSTEM_PLL2_333M = 27,
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CLK_SRC_SYSTEM_PLL2_250M = 28,
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CLK_SRC_SYSTEM_PLL2_200M = 29,
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CLK_SRC_SYSTEM_PLL2_166M = 30,
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CLK_SRC_SYSTEM_PLL2_125M = 31,
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CLK_SRC_SYSTEM_PLL2_100M = 32,
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CLK_SRC_SYSTEM_PLL2_50M = 33,
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CLK_SRC_SYSTEM_PLL3 = 34,
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CLK_SRC_AUDIO_PLL1 = 35,
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CLK_SRC_AUDIO_PLL2 = 36,
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CLK_SRC_VIDEO_PLL1 = 37,
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};
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#define INTPLL_LOCK_MASK BIT(31)
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#define INTPLL_LOCK_SEL_MASK BIT(29)
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#define INTPLL_EXT_BYPASS_MASK BIT(28)
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#define INTPLL_DIV20_CLKE_MASK BIT(27)
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#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
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#define INTPLL_DIV10_CLKE_MASK BIT(25)
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#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
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#define INTPLL_DIV8_CLKE_MASK BIT(23)
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#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
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#define INTPLL_DIV6_CLKE_MASK BIT(21)
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#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
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#define INTPLL_DIV5_CLKE_MASK BIT(19)
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#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
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#define INTPLL_DIV4_CLKE_MASK BIT(17)
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#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
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#define INTPLL_DIV3_CLKE_MASK BIT(15)
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#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
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#define INTPLL_DIV2_CLKE_MASK BIT(13)
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#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
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#define INTPLL_CLKE_MASK BIT(11)
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#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
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#define INTPLL_RST_MASK BIT(9)
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#define INTPLL_RST_OVERRIDE_MASK BIT(8)
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#define INTPLL_BYPASS_MASK BIT(4)
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#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
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#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
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#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
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#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
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#define INTPLL_MAIN_DIV_SHIFT 12
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#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
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#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
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#define INTPLL_PRE_DIV_SHIFT 4
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#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
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#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
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#define INTPLL_POST_DIV_SHIFT 0
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#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
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#define INTPLL_LOCK_CON_DLY_SHIFT 4
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#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
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#define INTPLL_LOCK_CON_OUT_SHIFT 2
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#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
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#define INTPLL_LOCK_CON_IN_SHIFT 0
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#define INTPLL_LRD_EN_MASK BIT(21)
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#define INTPLL_FOUT_MASK BIT(20)
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#define INTPLL_AFC_SEL_MASK BIT(19)
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#define INTPLL_PBIAS_CTRL_MASK BIT(18)
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#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
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#define INTPLL_AFCINIT_SEL_MASK BIT(16)
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#define INTPLL_FSEL_MASK BIT(14)
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#define INTPLL_FEED_EN_MASK BIT(13)
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#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
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#define INTPLL_AFC_EN_MASK BIT(2)
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#define INTPLL_ICP_MASK GENMASK(1, 0)
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#endif
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