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u-boot/arch/mips/lib
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Daniel Schwierzeck 5ef337a037 MIPS: cache: make index base address configurable 
The index base address used for the cache initialisation is currently
hard-coded to CKSEG0. Make this value configurable if a MIPS system
needs to have a different address (e.g. in SRAM or ScratchPad RAM).

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22 21:02:03 +02:00
..
ashldi3.c dm: mips: Import libgcc components from Linux 2012-08-17 20:13:48 +02:00
ashrdi3.c dm: mips: Import libgcc components from Linux 2012-08-17 20:13:48 +02:00
asm-offsets.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
bootm.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
cache.c MIPS: cache: reimplement dcache_[status, enable, disable] 2018-09-22 21:02:03 +02:00
cache_init.S MIPS: cache: make index base address configurable 2018-09-22 21:02:03 +02:00
genex.S SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
libgcc.h dm: mips: Import libgcc components from Linux 2012-08-17 20:13:48 +02:00
lshrdi3.c dm: mips: Import libgcc components from Linux 2012-08-17 20:13:48 +02:00
Makefile SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
reloc.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
stack.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
traps.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00