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https://github.com/AsahiLinux/u-boot
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ac0ba47b9c
Enable all types of non-secure access to PFE block registers. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
171 lines
4.1 KiB
C
171 lines
4.1 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_NS_ACCESS_H_
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#define __FSL_NS_ACCESS_H_
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#include <fsl_csu.h>
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enum csu_cslx_ind {
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CSU_CSLX_PCIE2_IO = 0,
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CSU_CSLX_PCIE1_IO,
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CSU_CSLX_MG2TPR_IP,
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CSU_CSLX_IFC_MEM,
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CSU_CSLX_OCRAM,
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CSU_CSLX_GIC,
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CSU_CSLX_PCIE1,
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CSU_CSLX_OCRAM2,
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CSU_CSLX_QSPI_MEM,
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CSU_CSLX_PCIE2,
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CSU_CSLX_SATA,
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CSU_CSLX_USB1,
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CSU_CSLX_QM_BM_SWPORTAL,
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CSU_CSLX_PCIE3 = 16,
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CSU_CSLX_PCIE3_IO,
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CSU_CSLX_USB3 = 20,
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CSU_CSLX_USB2,
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CSU_CSLX_PFE = 23,
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CSU_CSLX_SERDES = 32,
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CSU_CSLX_QDMA,
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CSU_CSLX_LPUART2,
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CSU_CSLX_LPUART1,
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CSU_CSLX_LPUART4,
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CSU_CSLX_LPUART3,
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CSU_CSLX_LPUART6,
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CSU_CSLX_LPUART5,
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CSU_CSLX_DSPI1 = 41,
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CSU_CSLX_QSPI,
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CSU_CSLX_ESDHC,
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CSU_CSLX_IFC = 45,
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CSU_CSLX_I2C1,
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CSU_CSLX_I2C3 = 48,
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CSU_CSLX_I2C2,
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CSU_CSLX_DUART2 = 50,
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CSU_CSLX_DUART1,
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CSU_CSLX_WDT2,
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CSU_CSLX_WDT1,
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CSU_CSLX_EDMA,
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CSU_CSLX_SYS_CNT,
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CSU_CSLX_DMA_MUX2,
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CSU_CSLX_DMA_MUX1,
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CSU_CSLX_DDR,
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CSU_CSLX_QUICC,
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CSU_CSLX_DCFG_CCU_RCPM = 60,
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CSU_CSLX_SECURE_BOOTROM,
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CSU_CSLX_SFP,
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CSU_CSLX_TMU,
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CSU_CSLX_SECURE_MONITOR,
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CSU_CSLX_SCFG,
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CSU_CSLX_FM = 66,
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CSU_CSLX_SEC5_5,
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CSU_CSLX_BM,
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CSU_CSLX_QM,
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CSU_CSLX_GPIO2 = 70,
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CSU_CSLX_GPIO1,
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CSU_CSLX_GPIO4,
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CSU_CSLX_GPIO3,
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CSU_CSLX_PLATFORM_CONT,
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CSU_CSLX_CSU,
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CSU_CSLX_IIC4 = 77,
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CSU_CSLX_WDT4,
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CSU_CSLX_WDT3,
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CSU_CSLX_ESDHC2 = 80,
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CSU_CSLX_WDT5 = 81,
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CSU_CSLX_SAI2,
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CSU_CSLX_SAI1,
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CSU_CSLX_SAI4,
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CSU_CSLX_SAI3,
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CSU_CSLX_FTM2 = 86,
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CSU_CSLX_FTM1,
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CSU_CSLX_FTM4,
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CSU_CSLX_FTM3,
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CSU_CSLX_FTM6 = 90,
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CSU_CSLX_FTM5,
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CSU_CSLX_FTM8,
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CSU_CSLX_FTM7,
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CSU_CSLX_DSCR = 121,
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};
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static struct csu_ns_dev ns_dev[] = {
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{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
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{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
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{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
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{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
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{CSU_CSLX_OCRAM, CSU_ALL_RW},
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{CSU_CSLX_GIC, CSU_ALL_RW},
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{CSU_CSLX_PCIE1, CSU_ALL_RW},
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{CSU_CSLX_OCRAM2, CSU_ALL_RW},
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{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
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{CSU_CSLX_PCIE2, CSU_ALL_RW},
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{CSU_CSLX_SATA, CSU_ALL_RW},
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{CSU_CSLX_USB1, CSU_ALL_RW},
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{CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
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{CSU_CSLX_PCIE3, CSU_ALL_RW},
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{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
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{CSU_CSLX_USB3, CSU_ALL_RW},
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{CSU_CSLX_USB2, CSU_ALL_RW},
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{CSU_CSLX_PFE, CSU_ALL_RW},
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{CSU_CSLX_SERDES, CSU_ALL_RW},
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{CSU_CSLX_QDMA, CSU_ALL_RW},
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{CSU_CSLX_LPUART2, CSU_ALL_RW},
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{CSU_CSLX_LPUART1, CSU_ALL_RW},
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{CSU_CSLX_LPUART4, CSU_ALL_RW},
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{CSU_CSLX_LPUART3, CSU_ALL_RW},
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{CSU_CSLX_LPUART6, CSU_ALL_RW},
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{CSU_CSLX_LPUART5, CSU_ALL_RW},
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{CSU_CSLX_DSPI1, CSU_ALL_RW},
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{CSU_CSLX_QSPI, CSU_ALL_RW},
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{CSU_CSLX_ESDHC, CSU_ALL_RW},
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{CSU_CSLX_IFC, CSU_ALL_RW},
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{CSU_CSLX_I2C1, CSU_ALL_RW},
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{CSU_CSLX_I2C3, CSU_ALL_RW},
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{CSU_CSLX_I2C2, CSU_ALL_RW},
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{CSU_CSLX_DUART2, CSU_ALL_RW},
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{CSU_CSLX_DUART1, CSU_ALL_RW},
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{CSU_CSLX_WDT2, CSU_ALL_RW},
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{CSU_CSLX_WDT1, CSU_ALL_RW},
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{CSU_CSLX_EDMA, CSU_ALL_RW},
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{CSU_CSLX_SYS_CNT, CSU_ALL_RW},
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{CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
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{CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
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{CSU_CSLX_DDR, CSU_ALL_RW},
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{CSU_CSLX_QUICC, CSU_ALL_RW},
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{CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
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{CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
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{CSU_CSLX_SFP, CSU_ALL_RW},
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{CSU_CSLX_TMU, CSU_ALL_RW},
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{CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
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{CSU_CSLX_SCFG, CSU_ALL_RW},
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{CSU_CSLX_FM, CSU_ALL_RW},
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{CSU_CSLX_SEC5_5, CSU_ALL_RW},
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{CSU_CSLX_BM, CSU_ALL_RW},
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{CSU_CSLX_QM, CSU_ALL_RW},
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{CSU_CSLX_GPIO2, CSU_ALL_RW},
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{CSU_CSLX_GPIO1, CSU_ALL_RW},
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{CSU_CSLX_GPIO4, CSU_ALL_RW},
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{CSU_CSLX_GPIO3, CSU_ALL_RW},
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{CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
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{CSU_CSLX_CSU, CSU_ALL_RW},
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{CSU_CSLX_IIC4, CSU_ALL_RW},
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{CSU_CSLX_WDT4, CSU_ALL_RW},
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{CSU_CSLX_WDT3, CSU_ALL_RW},
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{CSU_CSLX_ESDHC2, CSU_ALL_RW},
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{CSU_CSLX_WDT5, CSU_ALL_RW},
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{CSU_CSLX_SAI2, CSU_ALL_RW},
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{CSU_CSLX_SAI1, CSU_ALL_RW},
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{CSU_CSLX_SAI4, CSU_ALL_RW},
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{CSU_CSLX_SAI3, CSU_ALL_RW},
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{CSU_CSLX_FTM2, CSU_ALL_RW},
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{CSU_CSLX_FTM1, CSU_ALL_RW},
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{CSU_CSLX_FTM4, CSU_ALL_RW},
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{CSU_CSLX_FTM3, CSU_ALL_RW},
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{CSU_CSLX_FTM6, CSU_ALL_RW},
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{CSU_CSLX_FTM5, CSU_ALL_RW},
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{CSU_CSLX_FTM8, CSU_ALL_RW},
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{CSU_CSLX_FTM7, CSU_ALL_RW},
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{CSU_CSLX_DSCR, CSU_ALL_RW},
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};
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#endif
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