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3ae6030cf9
Rename platform_data include file as spi_pl022.h from pl022_spi.h, this is generic notation used for spi platdata include files. Acked-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
325 lines
7.4 KiB
C
325 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012
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* Armando Visconti, ST Microelectronics, armando.visconti@st.com.
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*
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* (C) Copyright 2018
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* Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
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*
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* Driver for ARM PL022 SPI Controller.
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <dm/platform_data/spi_pl022.h>
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#include <linux/io.h>
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#include <spi.h>
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#define SSP_CR0 0x000
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#define SSP_CR1 0x004
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#define SSP_DR 0x008
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#define SSP_SR 0x00C
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#define SSP_CPSR 0x010
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#define SSP_IMSC 0x014
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#define SSP_RIS 0x018
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#define SSP_MIS 0x01C
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#define SSP_ICR 0x020
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#define SSP_DMACR 0x024
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#define SSP_CSR 0x030 /* vendor extension */
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#define SSP_ITCR 0x080
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#define SSP_ITIP 0x084
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#define SSP_ITOP 0x088
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#define SSP_TDR 0x08C
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#define SSP_PID0 0xFE0
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#define SSP_PID1 0xFE4
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#define SSP_PID2 0xFE8
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#define SSP_PID3 0xFEC
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#define SSP_CID0 0xFF0
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#define SSP_CID1 0xFF4
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#define SSP_CID2 0xFF8
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#define SSP_CID3 0xFFC
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/* SSP Control Register 0 - SSP_CR0 */
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#define SSP_CR0_SPO (0x1 << 6)
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#define SSP_CR0_SPH (0x1 << 7)
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#define SSP_CR0_BIT_MODE(x) ((x) - 1)
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#define SSP_SCR_MIN (0x00)
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#define SSP_SCR_MAX (0xFF)
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#define SSP_SCR_SHFT 8
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#define DFLT_CLKRATE 2
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/* SSP Control Register 1 - SSP_CR1 */
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#define SSP_CR1_MASK_SSE (0x1 << 1)
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#define SSP_CPSR_MIN (0x02)
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#define SSP_CPSR_MAX (0xFE)
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#define DFLT_PRESCALE (0x40)
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/* SSP Status Register - SSP_SR */
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#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */
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#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */
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#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */
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#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */
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#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */
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struct pl022_spi_slave {
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void *base;
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unsigned int freq;
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};
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/*
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* ARM PL022 exists in different 'flavors'.
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* This drivers currently support the standard variant (0x00041022), that has a
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* 16bit wide and 8 locations deep TX/RX FIFO.
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*/
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static int pl022_is_supported(struct pl022_spi_slave *ps)
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{
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/* PL022 version is 0x00041022 */
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if ((readw(ps->base + SSP_PID0) == 0x22) &&
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(readw(ps->base + SSP_PID1) == 0x10) &&
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((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&
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(readw(ps->base + SSP_PID3) == 0x00))
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return 1;
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return 0;
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}
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static int pl022_spi_probe(struct udevice *bus)
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{
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struct pl022_spi_pdata *plat = dev_get_platdata(bus);
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struct pl022_spi_slave *ps = dev_get_priv(bus);
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ps->base = ioremap(plat->addr, plat->size);
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ps->freq = plat->freq;
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/* Check the PL022 version */
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if (!pl022_is_supported(ps))
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return -ENOTSUPP;
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/* 8 bits per word, high polarity and default clock rate */
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writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);
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writew(DFLT_PRESCALE, ps->base + SSP_CPSR);
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return 0;
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}
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static void flush(struct pl022_spi_slave *ps)
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{
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do {
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while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
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readw(ps->base + SSP_DR);
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} while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);
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}
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static int pl022_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct pl022_spi_slave *ps = dev_get_priv(bus);
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u16 reg;
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/* Enable the SPI hardware */
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reg = readw(ps->base + SSP_CR1);
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reg |= SSP_CR1_MASK_SSE;
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writew(reg, ps->base + SSP_CR1);
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flush(ps);
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return 0;
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}
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static int pl022_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct pl022_spi_slave *ps = dev_get_priv(bus);
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u16 reg;
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flush(ps);
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/* Disable the SPI hardware */
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reg = readw(ps->base + SSP_CR1);
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reg &= ~SSP_CR1_MASK_SSE;
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writew(reg, ps->base + SSP_CR1);
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return 0;
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}
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static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct pl022_spi_slave *ps = dev_get_priv(bus);
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u32 len_tx = 0, len_rx = 0, len;
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u32 ret = 0;
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const u8 *txp = dout;
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u8 *rxp = din, value;
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if (bitlen == 0)
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/* Finish any previously submitted transfers */
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return 0;
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/*
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* TODO: The controller can do non-multiple-of-8 bit
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* transfers, but this driver currently doesn't support it.
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*
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* It's also not clear how such transfers are supposed to be
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* represented as a stream of bytes...this is a limitation of
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* the current SPI interface.
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*/
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if (bitlen % 8) {
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/* Errors always terminate an ongoing transfer */
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flags |= SPI_XFER_END;
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return -1;
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}
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len = bitlen / 8;
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while (len_tx < len) {
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if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {
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value = txp ? *txp++ : 0;
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writew(value, ps->base + SSP_DR);
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len_tx++;
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}
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if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
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value = readw(ps->base + SSP_DR);
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if (rxp)
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*rxp++ = value;
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len_rx++;
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}
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}
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while (len_rx < len_tx) {
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if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
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value = readw(ps->base + SSP_DR);
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if (rxp)
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*rxp++ = value;
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len_rx++;
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}
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}
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return ret;
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}
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static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
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{
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return rate / (cpsdvsr * (1 + scr));
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}
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static int pl022_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct pl022_spi_slave *ps = dev_get_priv(bus);
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u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr,
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best_cpsr = cpsr;
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u32 min, max, best_freq = 0, tmp;
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u32 rate = ps->freq;
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bool found = false;
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max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);
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min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX);
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if (speed > max || speed < min) {
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pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",
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speed, min, max);
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return -EINVAL;
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}
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while (cpsr <= SSP_CPSR_MAX && !found) {
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while (scr <= SSP_SCR_MAX) {
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tmp = spi_rate(rate, cpsr, scr);
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if (abs(speed - tmp) < abs(speed - best_freq)) {
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best_freq = tmp;
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best_cpsr = cpsr;
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best_scr = scr;
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if (tmp == speed) {
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found = true;
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break;
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}
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}
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scr++;
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}
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cpsr += 2;
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scr = SSP_SCR_MIN;
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}
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writew(best_cpsr, ps->base + SSP_CPSR);
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cr0 = readw(ps->base + SSP_CR0);
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writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);
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return 0;
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}
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static int pl022_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct pl022_spi_slave *ps = dev_get_priv(bus);
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u16 reg;
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reg = readw(ps->base + SSP_CR0);
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reg &= ~(SSP_CR0_SPH | SSP_CR0_SPO);
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if (mode & SPI_CPHA)
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reg |= SSP_CR0_SPH;
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if (mode & SPI_CPOL)
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reg |= SSP_CR0_SPO;
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writew(reg, ps->base + SSP_CR0);
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return 0;
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}
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static int pl022_cs_info(struct udevice *bus, uint cs,
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struct spi_cs_info *info)
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{
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return 0;
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}
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static const struct dm_spi_ops pl022_spi_ops = {
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.claim_bus = pl022_spi_claim_bus,
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.release_bus = pl022_spi_release_bus,
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.xfer = pl022_spi_xfer,
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.set_speed = pl022_spi_set_speed,
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.set_mode = pl022_spi_set_mode,
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.cs_info = pl022_cs_info,
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};
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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static int pl022_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct pl022_spi_pdata *plat = bus->platdata;
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const void *fdt = gd->fdt_blob;
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int node = dev_of_offset(bus);
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struct clk clkdev;
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int ret;
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plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);
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ret = clk_get_by_index(bus, 0, &clkdev);
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if (ret)
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return ret;
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plat->freq = clk_get_rate(&clkdev);
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return 0;
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}
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static const struct udevice_id pl022_spi_ids[] = {
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{ .compatible = "arm,pl022-spi" },
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{ }
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};
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#endif
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U_BOOT_DRIVER(pl022_spi) = {
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.name = "pl022_spi",
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.id = UCLASS_SPI,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.of_match = pl022_spi_ids,
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.ofdata_to_platdata = pl022_spi_ofdata_to_platdata,
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#endif
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.ops = &pl022_spi_ops,
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.platdata_auto_alloc_size = sizeof(struct pl022_spi_pdata),
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.priv_auto_alloc_size = sizeof(struct pl022_spi_slave),
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.probe = pl022_spi_probe,
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};
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