mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
447 lines
11 KiB
C
447 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Microchip PIC32 SPI controller driver.
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*
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* Copyright (c) 2015, Microchip Technology Inc.
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* Purna Chandra Mandal <purna.mandal@microchip.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <linux/compat.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/types.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <dt-bindings/clock/microchip,clock.h>
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#include <mach/pic32.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* PIC32 SPI controller registers */
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struct pic32_reg_spi {
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struct pic32_reg_atomic ctrl;
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struct pic32_reg_atomic status;
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struct pic32_reg_atomic buf;
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struct pic32_reg_atomic baud;
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struct pic32_reg_atomic ctrl2;
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};
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/* Bit fields in SPI Control Register */
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#define PIC32_SPI_CTRL_MSTEN BIT(5) /* Enable SPI Master */
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#define PIC32_SPI_CTRL_CKP BIT(6) /* active low */
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#define PIC32_SPI_CTRL_CKE BIT(8) /* Tx on falling edge */
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#define PIC32_SPI_CTRL_SMP BIT(9) /* Rx at middle or end of tx */
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#define PIC32_SPI_CTRL_BPW_MASK 0x03 /* Bits per word */
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#define PIC32_SPI_CTRL_BPW_8 0x0
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#define PIC32_SPI_CTRL_BPW_16 0x1
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#define PIC32_SPI_CTRL_BPW_32 0x2
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#define PIC32_SPI_CTRL_BPW_SHIFT 10
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#define PIC32_SPI_CTRL_ON BIT(15) /* Macro enable */
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#define PIC32_SPI_CTRL_ENHBUF BIT(16) /* Enable enhanced buffering */
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#define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */
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#define PIC32_SPI_CTRL_MSSEN BIT(28) /* SPI macro will drive SS */
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#define PIC32_SPI_CTRL_FRMEN BIT(31) /* Enable framing mode */
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/* Bit fields in SPI Status Register */
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#define PIC32_SPI_STAT_RX_OV BIT(6) /* err, s/w needs to clear */
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#define PIC32_SPI_STAT_TF_LVL_MASK 0x1f
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#define PIC32_SPI_STAT_TF_LVL_SHIFT 16
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#define PIC32_SPI_STAT_RF_LVL_MASK 0x1f
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#define PIC32_SPI_STAT_RF_LVL_SHIFT 24
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/* Bit fields in SPI Baud Register */
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#define PIC32_SPI_BAUD_MASK 0x1ff
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struct pic32_spi_priv {
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struct pic32_reg_spi *regs;
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u32 fifo_depth; /* FIFO depth in bytes */
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u32 fifo_n_word; /* FIFO depth in words */
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struct gpio_desc cs_gpio;
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/* Current SPI slave specific */
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ulong clk_rate;
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u32 speed_hz; /* spi-clk rate */
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int mode;
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/* Current message/transfer state */
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const void *tx;
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const void *tx_end;
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const void *rx;
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const void *rx_end;
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u32 len;
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/* SPI FiFo accessor */
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void (*rx_fifo)(struct pic32_spi_priv *);
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void (*tx_fifo)(struct pic32_spi_priv *);
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};
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static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
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{
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writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
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}
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static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
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{
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writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
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}
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static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
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{
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u32 sr = readl(&priv->regs->status.raw);
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return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
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}
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static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
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{
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u32 sr = readl(&priv->regs->status.raw);
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return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
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}
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/* Return the max entries we can fill into tx fifo */
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static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
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{
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u32 tx_left, tx_room, rxtx_gap;
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tx_left = (priv->tx_end - priv->tx) / n_bytes;
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tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);
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rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
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rxtx_gap /= n_bytes;
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return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
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}
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/* Return the max entries we should read out of rx fifo */
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static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
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{
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u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;
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return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
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}
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#define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \
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static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv) \
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{ \
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__type val; \
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u32 mx = pic32_rx_max(priv, sizeof(__type)); \
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\
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for (; mx; mx--) { \
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val = read##__bwl(&priv->regs->buf.raw); \
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if (priv->rx_end - priv->len) \
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*(__type *)(priv->rx) = val; \
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priv->rx += sizeof(__type); \
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} \
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} \
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\
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static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv) \
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{ \
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__type val; \
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u32 mx = pic32_tx_max(priv, sizeof(__type)); \
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\
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for (; mx ; mx--) { \
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val = (__type) ~0U; \
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if (priv->tx_end - priv->len) \
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val = *(__type *)(priv->tx); \
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write##__bwl(val, &priv->regs->buf.raw); \
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priv->tx += sizeof(__type); \
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} \
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}
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BUILD_SPI_FIFO_RW(byte, u8, b);
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BUILD_SPI_FIFO_RW(word, u16, w);
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BUILD_SPI_FIFO_RW(dword, u32, l);
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static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
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unsigned int wordlen)
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{
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u32 bits_per_word;
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u32 val;
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switch (wordlen) {
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case 8:
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priv->rx_fifo = pic32_spi_rx_byte;
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priv->tx_fifo = pic32_spi_tx_byte;
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bits_per_word = PIC32_SPI_CTRL_BPW_8;
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break;
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case 16:
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priv->rx_fifo = pic32_spi_rx_word;
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priv->tx_fifo = pic32_spi_tx_word;
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bits_per_word = PIC32_SPI_CTRL_BPW_16;
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break;
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case 32:
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priv->rx_fifo = pic32_spi_rx_dword;
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priv->tx_fifo = pic32_spi_tx_dword;
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bits_per_word = PIC32_SPI_CTRL_BPW_32;
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break;
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default:
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printf("pic32-spi: unsupported wordlen\n");
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return -EINVAL;
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}
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/* set bits-per-word */
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val = readl(&priv->regs->ctrl.raw);
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val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
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val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
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writel(val, &priv->regs->ctrl.raw);
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/* calculate maximum number of words fifo can hold */
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priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);
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return 0;
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}
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static int pic32_spi_claim_bus(struct udevice *slave)
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{
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struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
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/* enable chip */
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pic32_spi_enable(priv);
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return 0;
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}
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static int pic32_spi_release_bus(struct udevice *slave)
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{
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struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
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/* disable chip */
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pic32_spi_disable(priv);
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return 0;
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}
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static void spi_cs_activate(struct pic32_spi_priv *priv)
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{
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if (!dm_gpio_is_valid(&priv->cs_gpio))
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return;
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dm_gpio_set_value(&priv->cs_gpio, 1);
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}
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static void spi_cs_deactivate(struct pic32_spi_priv *priv)
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{
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if (!dm_gpio_is_valid(&priv->cs_gpio))
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return;
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dm_gpio_set_value(&priv->cs_gpio, 0);
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}
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static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
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const void *tx_buf, void *rx_buf,
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unsigned long flags)
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{
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struct dm_spi_slave_platdata *slave_plat;
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struct udevice *bus = slave->parent;
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struct pic32_spi_priv *priv;
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int len = bitlen / 8;
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int ret = 0;
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ulong tbase;
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priv = dev_get_priv(bus);
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slave_plat = dev_get_parent_platdata(slave);
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debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
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bus->seq, slave_plat->cs, flags);
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debug("msg tx %p, rx %p submitted of %d byte(s)\n",
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tx_buf, rx_buf, len);
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/* assert cs */
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(priv);
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/* set current transfer information */
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priv->tx = tx_buf;
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priv->rx = rx_buf;
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priv->tx_end = priv->tx + len;
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priv->rx_end = priv->rx + len;
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priv->len = len;
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/* transact by polling */
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tbase = get_timer(0);
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for (;;) {
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priv->tx_fifo(priv);
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priv->rx_fifo(priv);
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/* received sufficient data */
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if (priv->rx >= priv->rx_end) {
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ret = 0;
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break;
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}
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if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
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printf("pic32_spi: error, xfer timedout.\n");
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flags |= SPI_XFER_END;
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ret = -ETIMEDOUT;
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break;
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}
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}
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/* deassert cs */
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(priv);
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return ret;
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}
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static int pic32_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct pic32_spi_priv *priv = dev_get_priv(bus);
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u32 div;
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debug("%s: %s, speed %u\n", __func__, bus->name, speed);
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/* div = [clk_in / (2 * spi_clk)] - 1 */
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div = (priv->clk_rate / 2 / speed) - 1;
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div &= PIC32_SPI_BAUD_MASK;
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writel(div, &priv->regs->baud.raw);
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priv->speed_hz = speed;
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return 0;
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}
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static int pic32_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct pic32_spi_priv *priv = dev_get_priv(bus);
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u32 val;
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debug("%s: %s, mode %d\n", __func__, bus->name, mode);
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/* set spi-clk mode */
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val = readl(&priv->regs->ctrl.raw);
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/* HIGH when idle */
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if (mode & SPI_CPOL)
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val |= PIC32_SPI_CTRL_CKP;
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else
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val &= ~PIC32_SPI_CTRL_CKP;
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/* TX at idle-to-active clk transition */
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if (mode & SPI_CPHA)
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val &= ~PIC32_SPI_CTRL_CKE;
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else
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val |= PIC32_SPI_CTRL_CKE;
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/* RX at end of tx */
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val |= PIC32_SPI_CTRL_SMP;
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writel(val, &priv->regs->ctrl.raw);
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priv->mode = mode;
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return 0;
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}
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static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
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{
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struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
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return pic32_spi_set_word_size(priv, wordlen);
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}
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static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
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{
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u32 val;
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/* disable module */
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pic32_spi_disable(priv);
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val = readl(&priv->regs->ctrl);
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/* enable enhanced fifo of 128bit deep */
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val |= PIC32_SPI_CTRL_ENHBUF;
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priv->fifo_depth = 16;
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/* disable framing mode */
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val &= ~PIC32_SPI_CTRL_FRMEN;
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/* enable master mode */
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val |= PIC32_SPI_CTRL_MSTEN;
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/* select clk source */
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val &= ~PIC32_SPI_CTRL_MCLKSEL;
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/* set manual /CS mode */
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val &= ~PIC32_SPI_CTRL_MSSEN;
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writel(val, &priv->regs->ctrl);
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/* clear rx overflow indicator */
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writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
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}
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static int pic32_spi_probe(struct udevice *bus)
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{
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struct pic32_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
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int node = dev_of_offset(bus);
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struct udevice *clkdev;
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fdt_addr_t addr;
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fdt_size_t size;
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int ret;
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debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq);
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addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = ioremap(addr, size);
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if (!priv->regs)
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return -EINVAL;
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dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency",
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250000000);
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/* get clock rate */
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ret = clk_get_by_index(bus, 0, &clkdev);
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if (ret < 0) {
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printf("pic32-spi: error, clk not found\n");
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return ret;
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}
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priv->clk_rate = clk_get_periph_rate(clkdev, ret);
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/* initialize HW */
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pic32_spi_hw_init(priv);
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/* set word len */
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pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
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/* PIC32 SPI controller can automatically drive /CS during transfer
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* depending on fifo fill-level. /CS will stay asserted as long as
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* TX fifo is non-empty, else will be deasserted confirming completion
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* of the ongoing transfer. To avoid this sort of error we will drive
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* /CS manually by toggling cs-gpio pins.
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*/
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ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
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&priv->cs_gpio, GPIOD_IS_OUT);
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if (ret) {
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printf("pic32-spi: error, cs-gpios not found\n");
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return ret;
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}
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return 0;
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}
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static const struct dm_spi_ops pic32_spi_ops = {
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.claim_bus = pic32_spi_claim_bus,
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.release_bus = pic32_spi_release_bus,
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.xfer = pic32_spi_xfer,
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.set_speed = pic32_spi_set_speed,
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.set_mode = pic32_spi_set_mode,
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.set_wordlen = pic32_spi_set_wordlen,
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};
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static const struct udevice_id pic32_spi_ids[] = {
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{ .compatible = "microchip,pic32mzda-spi" },
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{ }
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};
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U_BOOT_DRIVER(pic32_spi) = {
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.name = "pic32_spi",
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.id = UCLASS_SPI,
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.of_match = pic32_spi_ids,
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.ops = &pic32_spi_ops,
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.priv_auto_alloc_size = sizeof(struct pic32_spi_priv),
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.probe = pic32_spi_probe,
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};
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