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42d37450e5
This adds PCIe controller support for MT7623. This is adapted from the Linux version. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
279 lines
6.4 KiB
C
279 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek PCIe host controller driver.
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*
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* Copyright (c) 2017-2019 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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* Honghui Zhang <honghui.zhang@mediatek.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <pci.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <linux/iopoll.h>
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#include <linux/list.h>
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/* PCIe shared registers */
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#define PCIE_SYS_CFG 0x00
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#define PCIE_INT_ENABLE 0x0c
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#define PCIE_CFG_ADDR 0x20
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#define PCIE_CFG_DATA 0x24
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/* PCIe per port registers */
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#define PCIE_BAR0_SETUP 0x10
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#define PCIE_CLASS 0x34
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#define PCIE_LINK_STATUS 0x50
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#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
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#define PCIE_PORT_PERST(x) BIT(1 + (x))
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#define PCIE_PORT_LINKUP BIT(0)
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#define PCIE_BAR_MAP_MAX GENMASK(31, 16)
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#define PCIE_BAR_ENABLE BIT(0)
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#define PCIE_REVISION_ID BIT(0)
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#define PCIE_CLASS_CODE (0x60400 << 8)
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#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
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((((regn) >> 8) & GENMASK(3, 0)) << 24))
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#define PCIE_CONF_ADDR(regn, bdf) \
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(PCIE_CONF_REG(regn) | (bdf))
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/* MediaTek specific configuration registers */
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#define PCIE_FTS_NUM 0x70c
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#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
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#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
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#define PCIE_FC_CREDIT 0x73c
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#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
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#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
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struct mtk_pcie_port {
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void __iomem *base;
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struct list_head list;
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struct mtk_pcie *pcie;
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struct reset_ctl reset;
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struct clk sys_ck;
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struct phy phy;
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u32 slot;
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};
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struct mtk_pcie {
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void __iomem *base;
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struct clk free_ck;
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struct list_head ports;
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};
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static int mtk_pcie_config_address(struct udevice *udev, pci_dev_t bdf,
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uint offset, void **paddress)
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{
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struct mtk_pcie *pcie = dev_get_priv(udev);
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writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
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*paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
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return 0;
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}
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static int mtk_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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return pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
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bdf, offset, valuep, size);
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}
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static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
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bdf, offset, value, size);
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}
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static const struct dm_pci_ops mtk_pcie_ops = {
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.read_config = mtk_pcie_read_config,
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.write_config = mtk_pcie_write_config,
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};
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static void mtk_pcie_port_free(struct mtk_pcie_port *port)
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{
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list_del(&port->list);
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free(port);
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}
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static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
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{
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struct mtk_pcie *pcie = port->pcie;
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u32 slot = PCI_DEV(port->slot << 11);
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u32 val;
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int err;
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/* assert port PERST_N */
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setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
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/* de-assert port PERST_N */
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clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
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/* 100ms timeout value should be enough for Gen1/2 training */
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err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
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!!(val & PCIE_PORT_LINKUP), 100000);
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if (err)
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return -ETIMEDOUT;
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/* disable interrupt */
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clrbits_le32(pcie->base + PCIE_INT_ENABLE,
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PCIE_PORT_INT_EN(port->slot));
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/* map to all DDR region. We need to set it before cfg operation. */
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writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
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port->base + PCIE_BAR0_SETUP);
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/* configure class code and revision ID */
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writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
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/* configure FC credit */
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writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot),
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pcie->base + PCIE_CFG_ADDR);
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clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK,
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PCIE_FC_CREDIT_VAL(0x806c));
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/* configure RC FTS number to 250 when it leaves L0s */
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writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR);
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clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK,
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PCIE_FTS_NUM_L0(0x50));
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return 0;
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}
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static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
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{
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int err;
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err = clk_enable(&port->sys_ck);
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if (err)
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goto exit;
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err = reset_assert(&port->reset);
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if (err)
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goto exit;
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err = reset_deassert(&port->reset);
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if (err)
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goto exit;
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err = generic_phy_init(&port->phy);
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if (err)
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goto exit;
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err = generic_phy_power_on(&port->phy);
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if (err)
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goto exit;
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if (!mtk_pcie_startup_port(port))
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return;
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pr_err("Port%d link down\n", port->slot);
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exit:
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mtk_pcie_port_free(port);
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}
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static int mtk_pcie_parse_port(struct udevice *dev, u32 slot)
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{
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struct mtk_pcie *pcie = dev_get_priv(dev);
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struct mtk_pcie_port *port;
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char name[10];
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int err;
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port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
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if (!port)
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return -ENOMEM;
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snprintf(name, sizeof(name), "port%d", slot);
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port->base = dev_remap_addr_name(dev, name);
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if (!port->base)
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return -ENOENT;
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snprintf(name, sizeof(name), "sys_ck%d", slot);
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err = clk_get_by_name(dev, name, &port->sys_ck);
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if (err)
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return err;
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err = reset_get_by_index(dev, slot, &port->reset);
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if (err)
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return err;
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err = generic_phy_get_by_index(dev, slot, &port->phy);
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if (err)
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return err;
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port->slot = slot;
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port->pcie = pcie;
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INIT_LIST_HEAD(&port->list);
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list_add_tail(&port->list, &pcie->ports);
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return 0;
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}
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static int mtk_pcie_probe(struct udevice *dev)
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{
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struct mtk_pcie *pcie = dev_get_priv(dev);
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struct mtk_pcie_port *port, *tmp;
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ofnode subnode;
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int err;
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INIT_LIST_HEAD(&pcie->ports);
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pcie->base = dev_remap_addr_name(dev, "subsys");
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if (!pcie->base)
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return -ENOENT;
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err = clk_get_by_name(dev, "free_ck", &pcie->free_ck);
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if (err)
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return err;
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/* enable top level clock */
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err = clk_enable(&pcie->free_ck);
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if (err)
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return err;
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dev_for_each_subnode(subnode, dev) {
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struct fdt_pci_addr addr;
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u32 slot = 0;
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if (!ofnode_is_available(subnode))
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continue;
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err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
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if (err)
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return err;
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slot = PCI_DEV(addr.phys_hi);
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err = mtk_pcie_parse_port(dev, slot);
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if (err)
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return err;
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}
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/* enable each port, and then check link status */
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list_for_each_entry_safe(port, tmp, &pcie->ports, list)
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mtk_pcie_enable_port(port);
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return 0;
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}
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static const struct udevice_id mtk_pcie_ids[] = {
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{ .compatible = "mediatek,mt7623-pcie", },
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{ }
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};
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U_BOOT_DRIVER(pcie_mediatek) = {
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.name = "pcie_mediatek",
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.id = UCLASS_PCI,
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.of_match = mtk_pcie_ids,
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.ops = &mtk_pcie_ops,
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.probe = mtk_pcie_probe,
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.priv_auto_alloc_size = sizeof(struct mtk_pcie),
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};
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