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6664a0e5f3
The dm_gpio_set_value() routine sets signal logical level, with GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1 (asserted), while reset inactive value is 0 (de-asserted). Fix the reset toggle code to set the correct reset logic value. Reported-by: Sven Auhagen <sven.auhagen@voleatech.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
582 lines
17 KiB
C
582 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Marvell International Ltd.
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*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*
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* Based on:
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* - drivers/pci/pcie_imx.c
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* - drivers/pci/pci_mvebu.c
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* - drivers/pci/pcie_xilinx.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* PCI Config space registers */
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#define PCIE_CONFIG_BAR0 0x10
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#define PCIE_LINK_STATUS_REG 0x80
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#define PCIE_LINK_STATUS_SPEED_OFF 16
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#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
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#define PCIE_LINK_STATUS_WIDTH_OFF 20
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#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
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/* Resizable bar capability registers */
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#define RESIZABLE_BAR_CAP 0x250
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#define RESIZABLE_BAR_CTL0 0x254
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#define RESIZABLE_BAR_CTL1 0x258
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/* iATU registers */
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_CR2 0x908
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_LOWER_BASE 0x90C
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#define PCIE_ATU_UPPER_BASE 0x910
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#define PCIE_ATU_LIMIT 0x914
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#define PCIE_ATU_LOWER_TARGET 0x918
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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#define PCIE_LINK_CAPABILITY 0x7C
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#define PCIE_LINK_CTL_2 0xA0
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#define TARGET_LINK_SPEED_MASK 0xF
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#define LINK_SPEED_GEN_1 0x1
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#define LINK_SPEED_GEN_2 0x2
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#define LINK_SPEED_GEN_3 0x3
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#define PCIE_GEN3_RELATED 0x890
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#define GEN3_EQU_DISABLE (1 << 16)
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#define GEN3_ZRXDC_NON_COMP (1 << 0)
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#define PCIE_GEN3_EQU_CTRL 0x8A8
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#define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5)
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#define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4)
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#define PCIE_LINK_UP_TIMEOUT_MS 100
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#define PCIE_GLOBAL_CONTROL 0x8000
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#define PCIE_APP_LTSSM_EN (1 << 2)
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#define PCIE_DEVICE_TYPE_OFFSET (4)
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#define PCIE_DEVICE_TYPE_MASK (0xF)
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#define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */
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#define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */
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#define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */
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#define PCIE_GLOBAL_STATUS 0x8008
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#define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1)
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#define PCIE_GLB_STS_PHY_LINK_UP (1 << 9)
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#define PCIE_ARCACHE_TRC 0x8050
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#define PCIE_AWCACHE_TRC 0x8054
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#define ARCACHE_SHAREABLE_CACHEABLE 0x3511
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#define AWCACHE_SHAREABLE_CACHEABLE 0x5311
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#define LINK_SPEED_GEN_1 0x1
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#define LINK_SPEED_GEN_2 0x2
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#define LINK_SPEED_GEN_3 0x3
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/**
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* struct pcie_dw_mvebu - MVEBU DW PCIe controller state
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*
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* @ctrl_base: The base address of the register space
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* @cfg_base: The base address of the configuration space
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* @cfg_size: The size of the configuration space which is needed
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* as it gets written into the PCIE_ATU_LIMIT register
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* @first_busno: This driver supports multiple PCIe controllers.
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* first_busno stores the bus number of the PCIe root-port
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* number which may vary depending on the PCIe setup
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* (PEX switches etc).
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*/
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struct pcie_dw_mvebu {
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void *ctrl_base;
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void *cfg_base;
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fdt_size_t cfg_size;
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int first_busno;
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/* IO and MEM PCI regions */
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struct pci_region io;
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struct pci_region mem;
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};
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static int pcie_dw_get_link_speed(const void *regs_base)
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{
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return (readl(regs_base + PCIE_LINK_STATUS_REG) &
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PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
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}
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static int pcie_dw_get_link_width(const void *regs_base)
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{
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return (readl(regs_base + PCIE_LINK_STATUS_REG) &
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PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
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}
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/**
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* pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
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*
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* @pcie: Pointer to the PCI controller state
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* @index: ATU region index
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* @type: ATU accsess type
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* @cpu_addr: the physical address for the translation entry
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* @pci_addr: the pcie bus address for the translation entry
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* @size: the size of the translation entry
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*/
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static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
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int type, u64 cpu_addr, u64 pci_addr,
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u32 size)
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{
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writel(PCIE_ATU_REGION_OUTBOUND | index,
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pcie->ctrl_base + PCIE_ATU_VIEWPORT);
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writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
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writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
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writel(lower_32_bits(cpu_addr + size - 1),
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pcie->ctrl_base + PCIE_ATU_LIMIT);
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writel(lower_32_bits(pci_addr),
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pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
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writel(upper_32_bits(pci_addr),
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pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
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writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
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writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
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}
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/**
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* set_cfg_address() - Configure the PCIe controller config space access
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*
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* @pcie: Pointer to the PCI controller state
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* @d: PCI device to access
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* @where: Offset in the configuration space
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*
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* Configures the PCIe controller to access the configuration space of
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* a specific PCIe device and returns the address to use for this
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* access.
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*
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* Return: Address that can be used to access the configation space
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* of the requested device / offset
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*/
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static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
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pci_dev_t d, uint where)
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{
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uintptr_t va_address;
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u32 atu_type;
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/*
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* Region #0 is used for Outbound CFG space access.
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* Direction = Outbound
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* Region Index = 0
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*/
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if (PCI_BUS(d) == (pcie->first_busno + 1))
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/* For local bus, change TLP Type field to 4. */
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atu_type = PCIE_ATU_TYPE_CFG0;
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else
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/* Otherwise, change TLP Type field to 5. */
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atu_type = PCIE_ATU_TYPE_CFG1;
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if (PCI_BUS(d) == pcie->first_busno) {
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/* Accessing root port configuration space. */
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va_address = (uintptr_t)pcie->ctrl_base;
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} else {
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d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
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pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
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atu_type, (u64)pcie->cfg_base,
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d << 8, pcie->cfg_size);
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va_address = (uintptr_t)pcie->cfg_base;
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}
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va_address += where & ~0x3;
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return va_address;
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}
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/**
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* pcie_dw_addr_valid() - Check for valid bus address
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*
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* @d: The PCI device to access
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* @first_busno: Bus number of the PCIe controller root complex
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*
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* Return 1 (true) if the PCI device can be accessed by this controller.
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*
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* Return: 1 on valid, 0 on invalid
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*/
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static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
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{
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if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
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return 0;
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if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
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return 0;
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return 1;
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}
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/**
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* pcie_dw_mvebu_read_config() - Read from configuration space
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*
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @valuep: A pointer at which to store the read value
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* @size: Indicates the size of access to perform
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*
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* Read a value of size @size from offset @offset within the configuration
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* space of the device identified by the bus, device & function numbers in @bdf
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* on the PCI bus @bus.
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*
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* Return: 0 on success
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*/
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static int pcie_dw_mvebu_read_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
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uintptr_t va_address;
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ulong value;
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debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
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debug("- out of range\n");
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*valuep = pci_get_ff(size);
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return 0;
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}
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va_address = set_cfg_address(pcie, bdf, offset);
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value = readl(va_address);
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debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
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*valuep = pci_conv_32_to_size(value, offset, size);
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pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_IO, pcie->io.phys_start,
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pcie->io.bus_start, pcie->io.size);
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return 0;
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}
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/**
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* pcie_dw_mvebu_write_config() - Write to configuration space
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*
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @value: The value to write
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* @size: Indicates the size of access to perform
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*
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* Write the value @value of size @size from offset @offset within the
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* configuration space of the device identified by the bus, device & function
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* numbers in @bdf on the PCI bus @bus.
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*
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* Return: 0 on success
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*/
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static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
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uintptr_t va_address;
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ulong old;
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debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
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if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
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debug("- out of range\n");
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return 0;
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}
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va_address = set_cfg_address(pcie, bdf, offset);
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old = readl(va_address);
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value = pci_conv_size_to_32(old, value, offset, size);
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writel(value, va_address);
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pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_IO, pcie->io.phys_start,
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pcie->io.bus_start, pcie->io.size);
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return 0;
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}
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/**
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* pcie_dw_configure() - Configure link capabilities and speed
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*
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* @regs_base: A pointer to the PCIe controller registers
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* @cap_speed: The capabilities and speed to configure
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*
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* Configure the link capabilities and speed in the PCIe root complex.
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*/
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static void pcie_dw_configure(const void *regs_base, u32 cap_speed)
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{
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/*
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* TODO (shadi@marvell.com, sr@denx.de):
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* Need to read the serdes speed from the dts and according to it
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* configure the PCIe gen
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*/
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/* Set link to GEN 3 */
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clrsetbits_le32(regs_base + PCIE_LINK_CTL_2,
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TARGET_LINK_SPEED_MASK, cap_speed);
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clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY,
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TARGET_LINK_SPEED_MASK, cap_speed);
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setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE);
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}
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/**
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* is_link_up() - Return the link state
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*
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* @regs_base: A pointer to the PCIe controller registers
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*
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* Return: 1 (true) for active line and 0 (false) for no link
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*/
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static int is_link_up(const void *regs_base)
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{
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u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
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u32 reg;
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reg = readl(regs_base + PCIE_GLOBAL_STATUS);
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if ((reg & mask) == mask)
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return 1;
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return 0;
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}
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/**
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* wait_link_up() - Wait for the link to come up
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*
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* @regs_base: A pointer to the PCIe controller registers
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*
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* Return: 1 (true) for active line and 0 (false) for no link (timeout)
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*/
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static int wait_link_up(const void *regs_base)
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{
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unsigned long timeout;
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timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
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while (!is_link_up(regs_base)) {
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if (get_timer(0) > timeout)
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return 0;
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};
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return 1;
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}
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/**
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* pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
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*
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* @regs_base: A pointer to the PCIe controller registers
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* @cap_speed: The capabilities and speed to configure
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*
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* Configure the PCIe controller root complex depending on the
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* requested link capabilities and speed.
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*
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* Return: 1 (true) for active line and 0 (false) for no link
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*/
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static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
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{
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if (!is_link_up(regs_base)) {
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/* Disable LTSSM state machine to enable configuration */
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clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
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PCIE_APP_LTSSM_EN);
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}
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clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
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PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET,
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PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET);
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/* Set the PCIe master AXI attributes */
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writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC);
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writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC);
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/* DW pre link configurations */
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pcie_dw_configure(regs_base, cap_speed);
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if (!is_link_up(regs_base)) {
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/* Configuration done. Start LTSSM */
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setbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
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PCIE_APP_LTSSM_EN);
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}
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/* Check that link was established */
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if (!wait_link_up(regs_base))
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return 0;
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/*
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* Link can be established in Gen 1. still need to wait
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* till MAC nagaotiation is completed
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*/
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udelay(100);
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return 1;
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}
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/**
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* pcie_dw_set_host_bars() - Configure the host BARs
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*
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* @regs_base: A pointer to the PCIe controller registers
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*
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* Configure the host BARs of the PCIe controller root port so that
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* PCI(e) devices may access the system memory.
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*/
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static void pcie_dw_set_host_bars(const void *regs_base)
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{
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u32 size = gd->ram_size;
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u64 max_size;
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u32 reg;
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u32 bar0;
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/* Verify the maximal BAR size */
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reg = readl(regs_base + RESIZABLE_BAR_CAP);
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max_size = 1ULL << (5 + (reg + (1 << 4)));
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if (size > max_size) {
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size = max_size;
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printf("Warning: PCIe BARs can't map all DRAM space\n");
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}
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/* Set the BAR base and size towards DDR */
|
|
bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
|
|
bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
|
|
writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
|
|
|
|
reg = ((size >> 20) - 1) << 12;
|
|
writel(size, regs_base + RESIZABLE_BAR_CTL0);
|
|
}
|
|
|
|
/**
|
|
* pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
|
|
*
|
|
* @dev: A pointer to the device being operated on
|
|
*
|
|
* Probe for an active link on the PCIe bus and configure the controller
|
|
* to enable this port.
|
|
*
|
|
* Return: 0 on success, else -ENODEV
|
|
*/
|
|
static int pcie_dw_mvebu_probe(struct udevice *dev)
|
|
{
|
|
struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
|
|
struct udevice *ctlr = pci_get_controller(dev);
|
|
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
|
|
#ifdef CONFIG_DM_GPIO
|
|
struct gpio_desc reset_gpio;
|
|
|
|
gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,
|
|
GPIOD_IS_OUT);
|
|
/*
|
|
* Issue reset to add-in card trough the dedicated GPIO.
|
|
* Some boards are connecting the card reset pin to common system
|
|
* reset wire and others are using separate GPIO port.
|
|
* In the last case we have to release a reset of the addon card
|
|
* using this GPIO.
|
|
*/
|
|
if (dm_gpio_is_valid(&reset_gpio)) {
|
|
dm_gpio_set_value(&reset_gpio, 1); /* assert */
|
|
mdelay(200);
|
|
dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
|
|
mdelay(200);
|
|
}
|
|
#else
|
|
debug("PCIE Reset on GPIO support is missing\n");
|
|
#endif /* CONFIG_DM_GPIO */
|
|
|
|
pcie->first_busno = dev->seq;
|
|
|
|
/* Don't register host if link is down */
|
|
if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
|
|
printf("PCIE-%d: Link down\n", dev->seq);
|
|
} else {
|
|
printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,
|
|
pcie_dw_get_link_speed(pcie->ctrl_base),
|
|
pcie_dw_get_link_width(pcie->ctrl_base),
|
|
hose->first_busno);
|
|
}
|
|
|
|
/* Store the IO and MEM windows settings for future use by the ATU */
|
|
pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
|
|
pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
|
|
pcie->io.size = hose->regions[0].size; /* IO size */
|
|
|
|
pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
|
|
pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
|
|
pcie->mem.size = hose->regions[1].size; /* MEM size */
|
|
|
|
pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
|
|
PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
|
|
pcie->mem.bus_start, pcie->mem.size);
|
|
|
|
/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
|
|
clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
|
|
0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16);
|
|
|
|
pcie_dw_set_host_bars(pcie->ctrl_base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pcie_dw_mvebu_ofdata_to_platdata() - Translate from DT to device state
|
|
*
|
|
* @dev: A pointer to the device being operated on
|
|
*
|
|
* Translate relevant data from the device tree pertaining to device @dev into
|
|
* state that the driver will later make use of. This state is stored in the
|
|
* device's private data structure.
|
|
*
|
|
* Return: 0 on success, else -EINVAL
|
|
*/
|
|
static int pcie_dw_mvebu_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
|
|
|
|
/* Get the controller base address */
|
|
pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0);
|
|
if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
/* Get the config space base address and size */
|
|
pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,
|
|
&pcie->cfg_size);
|
|
if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_pci_ops pcie_dw_mvebu_ops = {
|
|
.read_config = pcie_dw_mvebu_read_config,
|
|
.write_config = pcie_dw_mvebu_write_config,
|
|
};
|
|
|
|
static const struct udevice_id pcie_dw_mvebu_ids[] = {
|
|
{ .compatible = "marvell,armada8k-pcie" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pcie_dw_mvebu) = {
|
|
.name = "pcie_dw_mvebu",
|
|
.id = UCLASS_PCI,
|
|
.of_match = pcie_dw_mvebu_ids,
|
|
.ops = &pcie_dw_mvebu_ops,
|
|
.ofdata_to_platdata = pcie_dw_mvebu_ofdata_to_platdata,
|
|
.probe = pcie_dw_mvebu_probe,
|
|
.priv_auto_alloc_size = sizeof(struct pcie_dw_mvebu),
|
|
};
|