mirror of
https://github.com/AsahiLinux/u-boot
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122 lines
2.9 KiB
C
122 lines
2.9 KiB
C
/*
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* (C) Copyright 2008
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <spd_sdram.h>
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Autodetect onboard DDR SDRAM on 85xx platforms
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*
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* NOTE: Some of the hardcoded values are hardware dependant,
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* so this should be extended for other future boards
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* using this routine!
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*/
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long int sdram_setup(int casl)
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{
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volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
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/*
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* Disable memory controller.
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*/
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ddr->cs0_config = 0;
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ddr->sdram_cfg = 0;
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ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
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ddr->cs0_config = CFG_DDR_CS0_CONFIG;
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ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
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ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
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ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
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ddr->sdram_mode = CFG_DDR_MODE;
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ddr->sdram_interval = CFG_DDR_INTERVAL;
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ddr->sdram_cfg_2 = CFG_DDR_CONFIG_2;
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ddr->sdram_clk_cntl = CFG_DDR_CLK_CONTROL;
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asm ("sync;isync;msync");
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udelay(1000);
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ddr->sdram_cfg = CFG_DDR_CONFIG;
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asm ("sync; isync; msync");
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udelay(1000);
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if (get_ram_size(0, CFG_SDRAM_SIZE<<20) == CFG_SDRAM_SIZE<<20) {
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/*
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* OK, size detected -> all done
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*/
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return CFG_SDRAM_SIZE<<20;
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}
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return 0; /* nothing found ! */
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}
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#endif
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long int initdram (int board_type)
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{
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long dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram ();
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#else
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dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
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#endif
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return dram_size;
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}
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) CFG_MEMTEST_START;
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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printf ("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf ("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf ("SDRAM test passed.\n");
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return 0;
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}
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#endif
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