mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 05:04:26 +00:00
7682a99826
Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
54 lines
890 B
ArmAsm
54 lines
890 B
ArmAsm
/*
|
|
* Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <config.h>
|
|
#include <command.h>
|
|
#include <mpc8xx.h>
|
|
|
|
#include <ppc_asm.tmpl>
|
|
#include <ppc_defs.h>
|
|
|
|
#include <asm/cache.h>
|
|
#include <asm/mmu.h>
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
|
|
/*
|
|
* cache flushing routines for kgdb
|
|
*/
|
|
|
|
.globl kgdb_flush_cache_all
|
|
kgdb_flush_cache_all:
|
|
lis r3, IDC_INVALL@h
|
|
mtspr DC_CST, r3
|
|
sync
|
|
lis r3, IDC_INVALL@h
|
|
mtspr IC_CST, r3
|
|
SYNC
|
|
blr
|
|
|
|
.globl kgdb_flush_cache_range
|
|
kgdb_flush_cache_range:
|
|
li r5,CONFIG_SYS_CACHELINE_SIZE-1
|
|
andc r3,r3,r5
|
|
subf r4,r3,r4
|
|
add r4,r4,r5
|
|
srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
|
|
beqlr
|
|
mtctr r4
|
|
mr r6,r3
|
|
1: dcbst 0,r3
|
|
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
|
|
bdnz 1b
|
|
sync /* wait for dcbst's to get to ram */
|
|
mtctr r4
|
|
2: icbi 0,r6
|
|
addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
|
|
bdnz 2b
|
|
SYNC
|
|
blr
|
|
|
|
#endif
|