mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 05:04:26 +00:00
9eb7acef97
Move arch/arm/include/asm/arch-uniphier/* -> arch/arm/mach-uniphier/include/mach/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
109 lines
2.9 KiB
C
109 lines
2.9 KiB
C
/*
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* UniPhier SBC (System Bus Controller) registers
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*
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* Copyright (C) 2011-2014 Panasonic Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef ARCH_SBC_REGS_H
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#define ARCH_SBC_REGS_H
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#define SBBASE_BASE 0x58c00100
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#define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
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#define SBBASE0 (SBBASE(0))
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#define SBBASE1 (SBBASE(1))
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#define SBBASE2 (SBBASE(2))
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#define SBBASE3 (SBBASE(3))
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#define SBBASE4 (SBBASE(4))
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#define SBBASE5 (SBBASE(5))
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#define SBBASE6 (SBBASE(6))
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#define SBBASE7 (SBBASE(7))
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#define SBBASE_BANK_ENABLE (0x00000001)
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#define SBCTRL_BASE 0x58c00200
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#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
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#define SBCTRL00 SBCTRL(0, 0)
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#define SBCTRL01 SBCTRL(0, 1)
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#define SBCTRL02 SBCTRL(0, 2)
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#define SBCTRL03 SBCTRL(0, 3)
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#define SBCTRL04 (SBCTRL_BASE + 0x100)
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#define SBCTRL10 SBCTRL(1, 0)
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#define SBCTRL11 SBCTRL(1, 1)
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#define SBCTRL12 SBCTRL(1, 2)
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#define SBCTRL13 SBCTRL(1, 3)
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#define SBCTRL14 (SBCTRL_BASE + 0x110)
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#define SBCTRL20 SBCTRL(2, 0)
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#define SBCTRL21 SBCTRL(2, 1)
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#define SBCTRL22 SBCTRL(2, 2)
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#define SBCTRL23 SBCTRL(2, 3)
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#define SBCTRL24 (SBCTRL_BASE + 0x120)
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#define SBCTRL30 SBCTRL(3, 0)
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#define SBCTRL31 SBCTRL(3, 1)
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#define SBCTRL32 SBCTRL(3, 2)
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#define SBCTRL33 SBCTRL(3, 3)
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#define SBCTRL34 (SBCTRL_BASE + 0x130)
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#define SBCTRL40 SBCTRL(4, 0)
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#define SBCTRL41 SBCTRL(4, 1)
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#define SBCTRL42 SBCTRL(4, 2)
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#define SBCTRL43 SBCTRL(4, 3)
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#define SBCTRL44 (SBCTRL_BASE + 0x140)
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#define SBCTRL50 SBCTRL(5, 0)
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#define SBCTRL51 SBCTRL(5, 1)
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#define SBCTRL52 SBCTRL(5, 2)
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#define SBCTRL53 SBCTRL(5, 3)
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#define SBCTRL54 (SBCTRL_BASE + 0x150)
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#define SBCTRL60 SBCTRL(6, 0)
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#define SBCTRL61 SBCTRL(6, 1)
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#define SBCTRL62 SBCTRL(6, 2)
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#define SBCTRL63 SBCTRL(6, 3)
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#define SBCTRL64 (SBCTRL_BASE + 0x160)
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#define SBCTRL70 SBCTRL(7, 0)
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#define SBCTRL71 SBCTRL(7, 1)
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#define SBCTRL72 SBCTRL(7, 2)
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#define SBCTRL73 SBCTRL(7, 3)
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#define SBCTRL74 (SBCTRL_BASE + 0x170)
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/* slower but LED works */
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#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
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#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
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#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
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#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
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/* faster but LED does not work */
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#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
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#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
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/* NOR flash needs more wait counts than SRAM */
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#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
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#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
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#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
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#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
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#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
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#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
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#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
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#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
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#define PC0CTRL 0x598000c0
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#define ROM_BOOT_ROMRSV2 0x59801208
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#ifndef __ASSEMBLY__
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#include <asm/io.h>
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static inline int boot_is_swapped(void)
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{
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return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
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}
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#endif
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#endif /* ARCH_SBC_REGS_H */
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