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999c6baf79
These headers define the Tegra124 hardware. Add them to the usual place. Add Tegra124 chip ID/SKU ID definitions to common headers. There's no real HW change on Tegra124 for 90% of the toys, so it might make sense for a future patch to unify some of the content of these files in a common location. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
25 lines
668 B
C
25 lines
668 B
C
/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA_GP_PADCTRL_H_
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#define _TEGRA_GP_PADCTRL_H_
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#define GP_HIDREV 0x804
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/* bit fields definitions for APB_MISC_GP_HIDREV register */
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#define HIDREV_CHIPID_SHIFT 8
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#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
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#define HIDREV_MAJORPREV_SHIFT 4
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#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
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/* CHIPID field returned from APB_MISC_GP_HIDREV register */
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#define CHIPID_TEGRA20 0x20
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#define CHIPID_TEGRA30 0x30
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#define CHIPID_TEGRA114 0x35
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#define CHIPID_TEGRA124 0x40
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#endif /* _TEGRA_GP_PADCTRL_H_ */
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