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7c587d320d
DaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs also. This patch moves common defines from arch-davinci/emac_defs.h to drivers/net/davinci_emac.h DaVinci specific PHY drivers hacked to include the new header. We might want to switch to phylib in future. Signed-off-by: Ilya Yanok <yanok@emcraft.com>
108 lines
3.5 KiB
C
108 lines
3.5 KiB
C
/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Based on:
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*
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* ----------------------------------------------------------------------------
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*
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* dm644x_emac.h
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*
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* TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
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*
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* Copyright (C) 2005 Texas Instruments.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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* Modifications:
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* ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
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*
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*/
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#ifndef _DM644X_EMAC_H_
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#define _DM644X_EMAC_H_
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#include <asm/arch/hardware.h>
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#ifdef CONFIG_SOC_DM365
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#define EMAC_BASE_ADDR (0x01d07000)
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#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
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#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
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#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
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#define DAVINCI_EMAC_VERSION2
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#elif defined(CONFIG_SOC_DA8XX)
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#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
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#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
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#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
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#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
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#define DAVINCI_EMAC_VERSION2
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#else
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#define EMAC_BASE_ADDR (0x01c80000)
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#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
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#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
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#define EMAC_MDIO_BASE_ADDR (0x01c84000)
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#endif
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#ifdef CONFIG_SOC_DM646X
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#define DAVINCI_EMAC_VERSION2
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#define DAVINCI_EMAC_GIG_ENABLE
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#endif
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#ifdef CONFIG_SOC_DM646X
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/* MDIO module input frequency */
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#define EMAC_MDIO_BUS_FREQ 76500000
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/* MDIO clock output frequency */
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#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
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#elif defined(CONFIG_SOC_DM365)
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/* MDIO module input frequency */
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#define EMAC_MDIO_BUS_FREQ 121500000
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/* MDIO clock output frequency */
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#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
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#elif defined(CONFIG_SOC_DA8XX)
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/* MDIO module input frequency */
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#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
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/* MDIO clock output frequency */
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#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
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#else
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/* MDIO module input frequency */
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#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
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/* MDIO clock output frequency */
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#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
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#endif
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#define PHY_KSZ8873 (0x00221450)
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int ksz8873_is_phy_connected(int phy_addr);
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int ksz8873_get_link_speed(int phy_addr);
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int ksz8873_init_phy(int phy_addr);
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int ksz8873_auto_negotiate(int phy_addr);
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#define PHY_LXT972 (0x001378e2)
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int lxt972_is_phy_connected(int phy_addr);
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int lxt972_get_link_speed(int phy_addr);
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int lxt972_init_phy(int phy_addr);
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int lxt972_auto_negotiate(int phy_addr);
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#define PHY_DP83848 (0x20005c90)
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int dp83848_is_phy_connected(int phy_addr);
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int dp83848_get_link_speed(int phy_addr);
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int dp83848_init_phy(int phy_addr);
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int dp83848_auto_negotiate(int phy_addr);
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#define PHY_ET1011C (0x282f013)
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int et1011c_get_link_speed(int phy_addr);
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#endif /* _DM644X_EMAC_H_ */
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