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5e0404ff85
The current code in reserve_noncached() has two issues:
1) The first update of gd->start_addr_sp always rounds down to a section
start. However, the equivalent calculation in cache.c:noncached_init()
always first rounds up to a section start, then subtracts a section size.
These two calculations differ if the initial value is already rounded to
section alignment.
2) The second update of gd->start_addr_sp subtracts exactly
CONFIG_SYS_NONCACHED_MEMORY, whereas the equivalent calculation in
cache.c:noncached_init() rounds the noncached size up to section
alignment before subtracting it. The two calculations differ if the
noncached region size is not a multiple of the MMU section size.
In practice, one/both of those issues causes a practical problem on
Jetson TX1; U-Boot triggers a synchronous abort during initialization,
likely due to overlapping use of some memory region.
This change fixes both these issues by duplicating the exact calculations
from noncached_init() into reserve_noncached().
However, this fix assumes that gd->start_addr_sp on entry to
reserve_noncached() exactly matches mem_malloc_start on entry to
noncached_init(). I haven't traced the code to see whether it absolutely
guarantees this in all (or indeed any!) cases. Consequently, I added some
comments in the hope that this condition will continue to be true.
Fixes: 5f7adb5b1c ("board_f: reserve noncached space below malloc area")
Cc: Vikas Manocha <vikas.manocha@st.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
119 lines
2.7 KiB
C
119 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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/* for now: just dummy functions to satisfy the linker */
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#include <common.h>
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#include <malloc.h>
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/*
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* Flush range from all levels of d-cache/unified-cache.
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* Affects the range [start, start + size - 1].
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*/
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__weak void flush_cache(unsigned long start, unsigned long size)
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{
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flush_dcache_range(start, start + size);
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}
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/*
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* Default implementation:
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* do a range flush for the entire range
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*/
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__weak void flush_dcache_all(void)
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{
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flush_cache(0, ~0);
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}
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/*
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* Default implementation of enable_caches()
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* Real implementation should be in platform code
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*/
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__weak void enable_caches(void)
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{
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puts("WARNING: Caches not enabled\n");
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}
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__weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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/* An empty stub, real implementation should be in platform code */
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}
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__weak void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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/* An empty stub, real implementation should be in platform code */
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}
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int check_cache_range(unsigned long start, unsigned long stop)
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{
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int ok = 1;
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if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
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ok = 0;
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if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
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ok = 0;
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if (!ok) {
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warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
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start, stop);
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}
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return ok;
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}
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#ifdef CONFIG_SYS_NONCACHED_MEMORY
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/*
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* Reserve one MMU section worth of address space below the malloc() area that
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* will be mapped uncached.
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*/
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static unsigned long noncached_start;
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static unsigned long noncached_end;
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static unsigned long noncached_next;
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void noncached_init(void)
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{
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phys_addr_t start, end;
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size_t size;
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/* If this calculation changes, update board_f.c:reserve_noncached() */
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end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
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size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
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start = end - size;
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debug("mapping memory %pa-%pa non-cached\n", &start, &end);
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noncached_start = start;
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noncached_end = end;
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noncached_next = start;
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
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#endif
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}
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phys_addr_t noncached_alloc(size_t size, size_t align)
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{
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phys_addr_t next = ALIGN(noncached_next, align);
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if (next >= noncached_end || (noncached_end - next) < size)
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return 0;
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debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
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noncached_next = next + size;
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return next;
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}
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#endif /* CONFIG_SYS_NONCACHED_MEMORY */
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#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
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void invalidate_l2_cache(void)
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{
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unsigned int val = 0;
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asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
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: : "r" (val) : "cc");
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isb();
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}
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#endif
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