mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 11:33:32 +00:00
5d6a64f71d
This converts removes the following symbols: CONFIG_HAS_ETH0 CONFIG_HAS_ETH1 CONFIG_HAS_ETH2 CONFIG_HAS_ETH3 This is because at this point, only the ids8313 platform was using the code which was controlled by these symbols. In turn, this code already performs error checking on being able to perform the device tree fixup. Rather than convert these to Kconfig for a single platform, update the code to not need these checks and remove them from all the platforms they were unused on. Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
125 lines
3.6 KiB
C
125 lines
3.6 KiB
C
/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
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/* QE microcode/firmware address */
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/* between the u-boot partition and env */
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/*
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* System IO Config
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*/
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/* 0x14000180 SICR_1 */
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#ifndef CONFIG_SYS_SICRL
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#define CONFIG_SYS_SICRL (0 \
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| SICR_1_UART1_UART1RTS \
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| SICR_1_I2C_CKSTOP \
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| SICR_1_IRQ_A_IRQ \
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| SICR_1_IRQ_B_IRQ \
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| SICR_1_GPIO_A_GPIO \
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| SICR_1_GPIO_B_GPIO \
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| SICR_1_GPIO_C_GPIO \
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| SICR_1_GPIO_D_GPIO \
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| SICR_1_GPIO_E_GPIO \
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| SICR_1_GPIO_F_GPIO \
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| SICR_1_USB_A_UART2S \
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| SICR_1_USB_B_UART2RTS \
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| SICR_1_FEC1_FEC1 \
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| SICR_1_FEC2_FEC2 \
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)
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#endif
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/* 0x00080400 SICR_2 */
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#define CONFIG_SYS_SICRH (0 \
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| SICR_2_FEC3_FEC3 \
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| SICR_2_HDLC1_A_HDLC1 \
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| SICR_2_ELBC_A_LA \
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| SICR_2_ELBC_B_LCLK \
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| SICR_2_HDLC2_A_HDLC2 \
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| SICR_2_USB_D_GPIO \
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| SICR_2_PCI_PCI \
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| SICR_2_HDLC1_B_HDLC1 \
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| SICR_2_HDLC1_C_HDLC1 \
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| SICR_2_HDLC2_B_GPIO \
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| SICR_2_HDLC2_C_HDLC2 \
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| SICR_2_QUIESCE_B \
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)
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/* GPR_1 */
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#define CONFIG_SYS_GPR1 0x50008060
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#define CONFIG_SYS_GP1DIR 0x00000000
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#define CONFIG_SYS_GP1ODR 0x00000000
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#define CONFIG_SYS_GP2DIR 0xFF000000
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#define CONFIG_SYS_GP2ODR 0x00000000
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#define CONFIG_SYS_DDRCDR (\
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DDRCDR_EN | \
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DDRCDR_PZ_MAXZ | \
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DDRCDR_NZ_MAXZ | \
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DDRCDR_M_ODR)
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
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SDRAM_CFG_32_BE | \
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SDRAM_CFG_SREN | \
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SDRAM_CFG_HSE)
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
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(0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
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CSCONFIG_ODT_RD_NEVER | \
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CSCONFIG_ODT_WR_ONLY_CURRENT | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10)
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#define CONFIG_SYS_DDR_MODE 0x47860242
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#define CONFIG_SYS_DDR_MODE2 0x8080c000
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#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
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(0 << TIMING_CFG0_WWT_SHIFT) | \
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(0 << TIMING_CFG0_RRT_SHIFT) | \
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(3 << TIMING_CFG1_WRREC_SHIFT) | \
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(7 << TIMING_CFG1_REFREC_SHIFT) | \
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(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
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(3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
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(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
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(5 << TIMING_CFG2_CPO_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
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#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
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/* EEprom support */
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/* ethernet port connected to piggy (UEC2) */
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#define CONFIG_UEC_ETH2
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#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
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#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
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#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
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#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC2_PHY_ADDR 0
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#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
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