mirror of
https://github.com/AsahiLinux/u-boot
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5d68d2f41d
This converts the following to Kconfig: CONFIG_SYS_FLASH_ERASE_TOUT CONFIG_SYS_FLASH_LOCK_TOUT CONFIG_SYS_FLASH_UNLOCK_TOUT CONFIG_SYS_FLASH_WRITE_TOUT In practice, for two m68k platforms we move to hard-coding with a comment the timeout values, rather than try and make convoluted Kconfig logic. We add options for the write and erase options to the pic32 flash driver, as this driver does make use of them. Everywhere else these are unreferenced values. Signed-off-by: Tom Rini <trini@konsulko.com>
152 lines
4.7 KiB
C
152 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*/
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#ifndef _M5253DEMO_H
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#define _M5253DEMO_H
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#include <linux/stringify.h>
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#define CONFIG_SYS_UART_PORT (0)
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#define LDS_BOARD_TEXT \
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. = DEFINED(env_offset) ? env_offset : .; \
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env/embedded.o(.text*);
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#ifdef CONFIG_DRIVER_DM9000
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# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
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# define DM9000_IO CONFIG_DM9000_BASE
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# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
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# undef CONFIG_DM9000_DEBUG
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# define CONFIG_DM9000_BYTE_SWAPPED
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# define CONFIG_OVERWRITE_ETHADDR_ONCE
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# define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
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"loadaddr=10000\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr) ${u-boot}\0" \
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"upd=run load; run prog\0" \
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"prog=prot off 0xff800000 0xff82ffff;" \
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"era 0xff800000 0xff82ffff;" \
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"cp.b ${loadaddr} 0xff800000 ${filesize};" \
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"save\0" \
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""
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#endif
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#define CONFIG_HOSTNAME "M5253DEMO"
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/* I2C */
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#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
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#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
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#define CONFIG_SYS_I2C_PINMUX_SET (0)
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#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
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#define CONFIG_SYS_FAST_CLK
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#ifdef CONFIG_SYS_FAST_CLK
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# define CONFIG_SYS_PLLCR 0x1243E054
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# define CONFIG_SYS_CLK 140000000
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#else
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# define CONFIG_SYS_PLLCR 0x135a4140
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# define CONFIG_SYS_CLK 70000000
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#endif
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
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#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
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/*
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
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#define CONFIG_SYS_MONITOR_LEN 0x40000
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
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/* FLASH organization */
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#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
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#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
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#define FLASH_SST6401B 0x200
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#define SST_ID_xF6401B 0x236D236D
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#ifdef CONFIG_SYS_FLASH_CFI
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/*
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* Unable to use CFI driver, due to incompatible sector erase command by SST.
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* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
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* 0x30 is block erase in SST
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*/
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# define CONFIG_SYS_FLASH_SIZE 0x800000
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# define CONFIG_FLASH_CFI_LEGACY
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#else
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# define CONFIG_SYS_SST_SECT 2048
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# define CONFIG_SYS_SST_SECTSZ 0x1000
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#endif
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/* Cache Configuration */
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 4)
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
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#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
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CF_ADDRMASK(8) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
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CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
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CF_CACR_DBWE)
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/* Port configuration */
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#define CONFIG_SYS_FECI2C 0xF0
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#define CONFIG_SYS_CS0_BASE 0xFF800000
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#define CONFIG_SYS_CS0_MASK 0x007F0021
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#define CONFIG_SYS_CS0_CTRL 0x00001D80
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#define CONFIG_SYS_CS1_BASE 0xE0000000
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#define CONFIG_SYS_CS1_MASK 0x00000001
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#define CONFIG_SYS_CS1_CTRL 0x00003DD8
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/*-----------------------------------------------------------------------
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* Port configuration
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*/
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#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
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#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
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#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
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#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
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#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
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#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
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#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
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#endif /* _M5253DEMO_H */
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