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https://github.com/AsahiLinux/u-boot
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5d535aa40b
lx2160a rev1 and rev2 SoC has different pcie controller. The pcie controller device tree node fields "compatible" and registers names needs to be updated accordingly This change in device tree is handled as part of fdt fixups. These changes would only be applied if the soc revision is not rev1. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
704 lines
17 KiB
C
704 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include <i2c.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <fsl_ddr.h>
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#include <fsl_sec.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <linux/libfdt.h>
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#include <fsl-mc/fsl_mc.h>
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#include <env_internal.h>
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#include <efi_loader.h>
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#include <asm/arch/mmu.h>
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#include <hwconfig.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/config.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include "../common/qixis.h"
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#include "../common/vid.h"
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#include <fsl_immap.h>
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#ifdef CONFIG_EMC2305
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#include "../common/emc2305.h"
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#endif
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#ifdef CONFIG_TARGET_LX2160AQDS
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#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
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#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
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#define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
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#define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
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#define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
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#define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
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#define SDHC1_BASE_PMUX_DSPI 2
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#define SDHC2_BASE_PMUX_DSPI 2
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#define IIC5_PMUX_SPI3 3
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#endif /* CONFIG_TARGET_LX2160AQDS */
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DECLARE_GLOBAL_DATA_PTR;
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static struct pl01x_serial_platdata serial0 = {
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#if CONFIG_CONS_INDEX == 0
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.base = CONFIG_SYS_SERIAL0,
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#elif CONFIG_CONS_INDEX == 1
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.base = CONFIG_SYS_SERIAL1,
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#else
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#error "Unsupported console index value."
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#endif
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.type = TYPE_PL011,
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};
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U_BOOT_DEVICE(nxp_serial0) = {
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.name = "serial_pl01x",
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.platdata = &serial0,
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};
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static struct pl01x_serial_platdata serial1 = {
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.base = CONFIG_SYS_SERIAL1,
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.type = TYPE_PL011,
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};
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U_BOOT_DEVICE(nxp_serial1) = {
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.name = "serial_pl01x",
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.platdata = &serial1,
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};
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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#else
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
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if (!ret)
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ret = dm_i2c_write(dev, 0, &ch, 1);
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#endif
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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static void uart_get_clock(void)
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{
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serial0.clock = get_serial_clock();
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serial1.clock = get_serial_clock();
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}
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int board_early_init_f(void)
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{
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#ifdef CONFIG_SYS_I2C_EARLY_INIT
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i2c_early_init_f();
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#endif
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/* get required clock for UART IP */
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uart_get_clock();
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#ifdef CONFIG_EMC2305
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select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
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emc2305_init();
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set_fan_speed(I2C_EMC2305_PWM);
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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#endif
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fsl_lsch3_early_init_f();
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return 0;
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}
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#ifdef CONFIG_OF_BOARD_FIXUP
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int board_fix_fdt(void *fdt)
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{
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char *reg_names, *reg_name;
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int names_len, old_name_len, new_name_len, remaining_names_len;
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struct str_map {
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char *old_str;
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char *new_str;
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} reg_names_map[] = {
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{ "ccsr", "dip" },
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{ "pf_ctrl", "ctrl" }
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};
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int off = -1, i;
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if (IS_SVR_REV(get_svr(), 1, 0))
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return 0;
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off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
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while (off != -FDT_ERR_NOTFOUND) {
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fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
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strlen("fsl,ls-pcie") + 1);
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reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
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&names_len);
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if (!reg_names)
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continue;
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reg_name = reg_names;
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remaining_names_len = names_len - (reg_name - reg_names);
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for (i = 0; (i < ARRAY_SIZE(reg_names_map)) && names_len; i++) {
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old_name_len = strlen(reg_names_map[i].old_str);
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new_name_len = strlen(reg_names_map[i].new_str);
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if (memcmp(reg_name, reg_names_map[i].old_str,
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old_name_len) == 0) {
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/* first only leave required bytes for new_str
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* and copy rest of the string after it
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*/
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memcpy(reg_name + new_name_len,
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reg_name + old_name_len,
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remaining_names_len - old_name_len);
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/* Now copy new_str */
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memcpy(reg_name, reg_names_map[i].new_str,
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new_name_len);
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names_len -= old_name_len;
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names_len += new_name_len;
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}
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reg_name = memchr(reg_name, '\0', remaining_names_len);
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if (!reg_name)
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break;
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reg_name += 1;
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remaining_names_len = names_len -
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(reg_name - reg_names);
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}
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fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
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off = fdt_node_offset_by_compatible(fdt, off,
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"fsl,lx2160a-pcie");
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}
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return 0;
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}
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#endif
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#if defined(CONFIG_TARGET_LX2160AQDS)
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void esdhc_dspi_status_fixup(void *blob)
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{
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const char esdhc0_path[] = "/soc/esdhc@2140000";
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const char esdhc1_path[] = "/soc/esdhc@2150000";
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const char dspi0_path[] = "/soc/dspi@2100000";
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const char dspi1_path[] = "/soc/dspi@2110000";
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const char dspi2_path[] = "/soc/dspi@2120000";
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 sdhc1_base_pmux;
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u32 sdhc2_base_pmux;
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u32 iic5_pmux;
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/* Check RCW field sdhc1_base_pmux to enable/disable
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* esdhc0/dspi0 DT node
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*/
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sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
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& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
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sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
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if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
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do_fixup_by_path(blob, dspi0_path, "status", "okay",
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sizeof("okay"), 1);
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do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
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sizeof("disabled"), 1);
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} else {
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do_fixup_by_path(blob, esdhc0_path, "status", "okay",
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sizeof("okay"), 1);
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do_fixup_by_path(blob, dspi0_path, "status", "disabled",
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sizeof("disabled"), 1);
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}
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/* Check RCW field sdhc2_base_pmux to enable/disable
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* esdhc1/dspi1 DT node
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*/
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sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
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& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
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sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
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if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
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do_fixup_by_path(blob, dspi1_path, "status", "okay",
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sizeof("okay"), 1);
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do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
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sizeof("disabled"), 1);
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} else {
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do_fixup_by_path(blob, esdhc1_path, "status", "okay",
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sizeof("okay"), 1);
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do_fixup_by_path(blob, dspi1_path, "status", "disabled",
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sizeof("disabled"), 1);
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}
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/* Check RCW field IIC5 to enable dspi2 DT node */
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iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
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& FSL_CHASSIS3_IIC5_PMUX_MASK;
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iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
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if (iic5_pmux == IIC5_PMUX_SPI3) {
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do_fixup_by_path(blob, dspi2_path, "status", "okay",
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sizeof("okay"), 1);
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}
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}
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#endif
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int esdhc_status_fixup(void *blob, const char *compat)
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{
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#if defined(CONFIG_TARGET_LX2160AQDS)
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/* Enable esdhc and dspi DT nodes based on RCW fields */
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esdhc_dspi_status_fixup(blob);
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#else
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/* Enable both esdhc DT nodes for LX2160ARDB */
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do_fixup_by_compat(blob, compat, "status", "okay",
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sizeof("okay"), 1);
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#endif
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return 0;
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}
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#if defined(CONFIG_VID)
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int i2c_multiplexer_select_vid_channel(u8 channel)
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{
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return select_i2c_ch_pca9547(channel);
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}
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int init_func_vid(void)
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{
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if (adjust_vdd(0) < 0)
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printf("core voltage not adjusted\n");
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return 0;
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}
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#endif
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int checkboard(void)
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{
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enum boot_src src = get_boot_src();
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char buf[64];
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u8 sw;
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#ifdef CONFIG_TARGET_LX2160AQDS
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int clock;
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static const char *const freq[] = {"100", "125", "156.25",
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"161.13", "322.26", "", "", "",
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"", "", "", "", "", "", "",
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"100 separate SSCG"};
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#endif
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cpu_name(buf);
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#ifdef CONFIG_TARGET_LX2160AQDS
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printf("Board: %s-QDS, ", buf);
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#else
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printf("Board: %s-RDB, ", buf);
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#endif
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sw = QIXIS_READ(arch);
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printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
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if (src == BOOT_SOURCE_SD_MMC) {
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puts("SD\n");
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} else {
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
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switch (sw) {
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case 0:
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case 4:
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puts("FlexSPI DEV#0\n");
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break;
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case 1:
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puts("FlexSPI DEV#1\n");
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break;
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case 2:
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case 3:
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puts("FlexSPI EMU\n");
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break;
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default:
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printf("invalid setting, xmap: %d\n", sw);
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break;
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}
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}
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#ifdef CONFIG_TARGET_LX2160AQDS
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printf("FPGA: v%d (%s), build %d",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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/* the timestamp string contains "\n" at the end */
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printf(" on %s", qixis_read_time(buf));
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puts("SERDES1 Reference : ");
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sw = QIXIS_READ(brdcfg[2]);
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clock = sw >> 4;
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printf("Clock1 = %sMHz ", freq[clock]);
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clock = sw & 0x0f;
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printf("Clock2 = %sMHz", freq[clock]);
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sw = QIXIS_READ(brdcfg[3]);
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puts("\nSERDES2 Reference : ");
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clock = sw >> 4;
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printf("Clock1 = %sMHz ", freq[clock]);
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clock = sw & 0x0f;
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printf("Clock2 = %sMHz", freq[clock]);
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sw = QIXIS_READ(brdcfg[12]);
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puts("\nSERDES3 Reference : ");
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clock = sw >> 4;
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printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
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#else
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printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
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puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
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puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
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puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
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#endif
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return 0;
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}
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#ifdef CONFIG_TARGET_LX2160AQDS
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/*
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* implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
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*/
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u8 qixis_esdhc_detect_quirk(void)
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{
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/* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
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* SDHC1 Card ID:
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* Specifies the type of card installed in the SDHC1 adapter slot.
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* 000= (reserved)
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* 001= eMMC V4.5 adapter is installed.
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* 010= SD/MMC 3.3V adapter is installed.
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* 011= eMMC V4.4 adapter is installed.
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* 100= eMMC V5.0 adapter is installed.
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* 101= MMC card/Legacy (3.3V) adapter is installed.
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* 110= SDCard V2/V3 adapter installed.
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* 111= no adapter is installed.
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*/
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return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
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QIXIS_ESDHC_NO_ADAPTER);
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}
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int config_board_mux(void)
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{
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u8 reg11, reg5, reg13;
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 sdhc1_base_pmux;
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u32 sdhc2_base_pmux;
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u32 iic5_pmux;
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/* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
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* Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
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* Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
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* Qixis and remote systems are isolated from the I2C1 bus.
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* Processor connections are still available.
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* SPI2 CS2_B controls EN25S64 SPI memory device.
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* SPI3 CS2_B controls EN25S64 SPI memory device.
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* EC2 connects to PHY #2 using RGMII protocol.
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* CLK_OUT connects to FPGA for clock measurement.
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*/
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reg5 = QIXIS_READ(brdcfg[5]);
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reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
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QIXIS_WRITE(brdcfg[5], reg5);
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/* Check RCW field sdhc1_base_pmux
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* esdhc0 : sdhc1_base_pmux = 0
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* dspi0 : sdhc1_base_pmux = 2
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*/
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sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
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& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
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sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
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if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
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reg11 = QIXIS_READ(brdcfg[11]);
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reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
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QIXIS_WRITE(brdcfg[11], reg11);
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} else {
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/* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
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* {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
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* {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
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*/
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reg11 = QIXIS_READ(brdcfg[11]);
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reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
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QIXIS_WRITE(brdcfg[11], reg11);
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}
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/* Check RCW field sdhc2_base_pmux
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* esdhc1 : sdhc2_base_pmux = 0 (default)
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* dspi1 : sdhc2_base_pmux = 2
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*/
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sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
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& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
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sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
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if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
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reg13 = QIXIS_READ(brdcfg[13]);
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reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
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QIXIS_WRITE(brdcfg[13], reg13);
|
|
} else {
|
|
reg13 = QIXIS_READ(brdcfg[13]);
|
|
reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
|
|
QIXIS_WRITE(brdcfg[13], reg13);
|
|
}
|
|
|
|
/* Check RCW field IIC5 to enable dspi2 DT nodei
|
|
* dspi2: IIC5 = 3
|
|
*/
|
|
iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
|
|
& FSL_CHASSIS3_IIC5_PMUX_MASK;
|
|
iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
|
|
|
|
if (iic5_pmux == IIC5_PMUX_SPI3) {
|
|
/* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
|
|
reg11 = QIXIS_READ(brdcfg[11]);
|
|
reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
|
|
QIXIS_WRITE(brdcfg[11], reg11);
|
|
|
|
/* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
|
|
* {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
|
|
* {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
|
|
*/
|
|
reg11 = QIXIS_READ(brdcfg[11]);
|
|
reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
|
|
QIXIS_WRITE(brdcfg[11], reg11);
|
|
} else {
|
|
/* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
|
|
reg11 = QIXIS_READ(brdcfg[11]);
|
|
reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
|
|
QIXIS_WRITE(brdcfg[11], reg11);
|
|
|
|
/* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
|
|
* {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
|
|
* {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
|
|
*/
|
|
reg11 = QIXIS_READ(brdcfg[11]);
|
|
reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
|
|
QIXIS_WRITE(brdcfg[11], reg11);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#elif defined(CONFIG_TARGET_LX2160ARDB)
|
|
int config_board_mux(void)
|
|
{
|
|
u8 brdcfg;
|
|
|
|
brdcfg = QIXIS_READ(brdcfg[4]);
|
|
/* The BRDCFG4 register controls general board configuration.
|
|
*|-------------------------------------------|
|
|
*|Field | Function |
|
|
*|-------------------------------------------|
|
|
*|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
|
|
*|CAN_EN | 0= CAN transceivers are disabled. |
|
|
*| | 1= CAN transceivers are enabled. |
|
|
*|-------------------------------------------|
|
|
*/
|
|
brdcfg |= BIT_MASK(5);
|
|
QIXIS_WRITE(brdcfg[4], brdcfg);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
int config_board_mux(void)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
unsigned long get_board_sys_clk(void)
|
|
{
|
|
#ifdef CONFIG_TARGET_LX2160AQDS
|
|
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
|
|
|
|
switch (sysclk_conf & 0x03) {
|
|
case QIXIS_SYSCLK_100:
|
|
return 100000000;
|
|
case QIXIS_SYSCLK_125:
|
|
return 125000000;
|
|
case QIXIS_SYSCLK_133:
|
|
return 133333333;
|
|
}
|
|
return 100000000;
|
|
#else
|
|
return 100000000;
|
|
#endif
|
|
}
|
|
|
|
unsigned long get_board_ddr_clk(void)
|
|
{
|
|
#ifdef CONFIG_TARGET_LX2160AQDS
|
|
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
|
|
|
|
switch ((ddrclk_conf & 0x30) >> 4) {
|
|
case QIXIS_DDRCLK_100:
|
|
return 100000000;
|
|
case QIXIS_DDRCLK_125:
|
|
return 125000000;
|
|
case QIXIS_DDRCLK_133:
|
|
return 133333333;
|
|
}
|
|
return 100000000;
|
|
#else
|
|
return 100000000;
|
|
#endif
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
|
|
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
|
|
#endif
|
|
#ifdef CONFIG_ENV_IS_NOWHERE
|
|
gd->env_addr = (ulong)&default_environment[0];
|
|
#endif
|
|
|
|
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
|
|
|
#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
|
|
/* invert AQR107 IRQ pins polarity */
|
|
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_CAAM
|
|
sec_init();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
void detail_board_ddr_info(void)
|
|
{
|
|
int i;
|
|
u64 ddr_size = 0;
|
|
|
|
puts("\nDDR ");
|
|
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
|
|
ddr_size += gd->bd->bi_dram[i].size;
|
|
print_size(ddr_size, "");
|
|
print_ddr_info(0);
|
|
}
|
|
|
|
#if defined(CONFIG_ARCH_MISC_INIT)
|
|
int arch_misc_init(void)
|
|
{
|
|
config_board_mux();
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_MC_ENET
|
|
extern int fdt_fixup_board_phy(void *fdt);
|
|
|
|
void fdt_fixup_board_enet(void *fdt)
|
|
{
|
|
int offset;
|
|
|
|
offset = fdt_path_offset(fdt, "/soc/fsl-mc");
|
|
|
|
if (offset < 0)
|
|
offset = fdt_path_offset(fdt, "/fsl-mc");
|
|
|
|
if (offset < 0) {
|
|
printf("%s: fsl-mc node not found in device tree (error %d)\n",
|
|
__func__, offset);
|
|
return;
|
|
}
|
|
|
|
if (get_mc_boot_status() == 0 &&
|
|
(is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
|
|
fdt_status_okay(fdt, offset);
|
|
fdt_fixup_board_phy(fdt);
|
|
} else {
|
|
fdt_status_fail(fdt, offset);
|
|
}
|
|
}
|
|
|
|
void board_quiesce_devices(void)
|
|
{
|
|
fsl_mc_ldpaa_exit(gd->bd);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_OF_BOARD_SETUP
|
|
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
int i;
|
|
u16 mc_memory_bank = 0;
|
|
|
|
u64 *base;
|
|
u64 *size;
|
|
u64 mc_memory_base = 0;
|
|
u64 mc_memory_size = 0;
|
|
u16 total_memory_banks;
|
|
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
|
|
|
|
if (mc_memory_base != 0)
|
|
mc_memory_bank++;
|
|
|
|
total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
|
|
|
|
base = calloc(total_memory_banks, sizeof(u64));
|
|
size = calloc(total_memory_banks, sizeof(u64));
|
|
|
|
/* fixup DT for the three GPP DDR banks */
|
|
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
|
base[i] = gd->bd->bi_dram[i].start;
|
|
size[i] = gd->bd->bi_dram[i].size;
|
|
}
|
|
|
|
#ifdef CONFIG_RESV_RAM
|
|
/* reduce size if reserved memory is within this bank */
|
|
if (gd->arch.resv_ram >= base[0] &&
|
|
gd->arch.resv_ram < base[0] + size[0])
|
|
size[0] = gd->arch.resv_ram - base[0];
|
|
else if (gd->arch.resv_ram >= base[1] &&
|
|
gd->arch.resv_ram < base[1] + size[1])
|
|
size[1] = gd->arch.resv_ram - base[1];
|
|
else if (gd->arch.resv_ram >= base[2] &&
|
|
gd->arch.resv_ram < base[2] + size[2])
|
|
size[2] = gd->arch.resv_ram - base[2];
|
|
#endif
|
|
|
|
if (mc_memory_base != 0) {
|
|
for (i = 0; i <= total_memory_banks; i++) {
|
|
if (base[i] == 0 && size[i] == 0) {
|
|
base[i] = mc_memory_base;
|
|
size[i] = mc_memory_size;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
|
|
|
|
#ifdef CONFIG_USB
|
|
fsl_fdt_fixup_dr_usb(blob, bd);
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_MC_ENET
|
|
fdt_fsl_mc_fixup_iommu_map_entry(blob);
|
|
fdt_fixup_board_enet(blob);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
void qixis_dump_switch(void)
|
|
{
|
|
int i, nr_of_cfgsw;
|
|
|
|
QIXIS_WRITE(cms[0], 0x00);
|
|
nr_of_cfgsw = QIXIS_READ(cms[1]);
|
|
|
|
puts("DIP switch settings dump:\n");
|
|
for (i = 1; i <= nr_of_cfgsw; i++) {
|
|
QIXIS_WRITE(cms[0], i);
|
|
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
|
|
}
|
|
}
|