mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 20:54:31 +00:00
52923c6db7
AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
24 lines
614 B
C
24 lines
614 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright (C) 2017 Andes Technology Corporation
|
|
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
|
|
*/
|
|
|
|
#ifndef _ASM_RISCV_CACHE_H
|
|
#define _ASM_RISCV_CACHE_H
|
|
|
|
/* cache */
|
|
void cache_flush(void);
|
|
|
|
/*
|
|
* The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
|
|
* We use that value for aligning DMA buffers unless the board config has
|
|
* specified an alternate cache line size.
|
|
*/
|
|
#ifdef CONFIG_SYS_CACHELINE_SIZE
|
|
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
|
#else
|
|
#define ARCH_DMA_MINALIGN 32
|
|
#endif
|
|
|
|
#endif /* _ASM_RISCV_CACHE_H */
|