mirror of
https://github.com/AsahiLinux/u-boot
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7d80a9cd92
While in most cases CSF_SIZE is handled via Kconfig we have some i.MX8M
platforms that set the size based on the now-renamed CONFIG_SECURE_BOOT
symbol. Update things so that CSF_SIZE itself depends on IMX_HAB being
enabled and provide the default value for i.MX8M family of parts.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Ye Li <ye.li@nxp.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Fixes: d714a75fd4 ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Ye Li <ye.li@nxp.com>
126 lines
3.8 KiB
C
126 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020 Toradex
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*/
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#ifndef __VERDIN_IMX8MM_H
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#define __VERDIN_IMX8MM_H
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#include <asm/arch/imx-regs.h>
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#include <linux/sizes.h>
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#define CONFIG_SPL_MAX_SIZE (148 * 1024)
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#define CONFIG_SYS_MONITOR_LEN SZ_512K
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_STACK 0x920000
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#define CONFIG_SPL_BSS_START_ADDR 0x910000
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#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
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/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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#define CONFIG_MALLOC_F_ADDR 0x930000
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/* For RAW image gives a error info not panic */
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#endif
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#define MEM_LAYOUT_ENV_SETTINGS \
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"fdt_addr_r=0x44000000\0" \
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"kernel_addr_r=0x42000000\0" \
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"ramdisk_addr_r=0x46400000\0" \
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"scriptaddr=0x46000000\0"
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#define CONFIG_LOADADDR 0x40480000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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/* Enable Distro Boot */
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#ifndef CONFIG_SPL_BUILD
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#undef CONFIG_ISO_PARTITION
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#else
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#define BOOTENV
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#endif
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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MEM_LAYOUT_ENV_SETTINGS \
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"bootcmd_mfg=fastboot 0\0" \
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"console=ttymxc0\0" \
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"fdt_addr=0x43000000\0" \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"initrd_addr=0x43800000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_image=Image\0" \
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"netargs=setenv bootargs console=${console},${baudrate} " \
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"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
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"\0" \
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"nfsboot=run netargs; dhcp ${loadaddr} ${kernel_image}; " \
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"tftp ${fdt_addr} verdin/${fdtfile}; " \
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"booti ${loadaddr} - ${fdt_addr}\0" \
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"setup=setenv setupargs console=${console},${baudrate} " \
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"console=tty1 consoleblank=0 earlycon\0" \
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"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
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"if test \"$confirm\" = \"y\"; then " \
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"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
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"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \
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"${blkcnt}; fi\0"
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_ENV_IS_IN_MMC)
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/* Environment in eMMC, before config block at the end of 1st "boot sector" */
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#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */
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#define CONFIG_SYS_MMC_ENV_PART 1
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#endif
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN SZ_32M
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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/* SDRAM configuration */
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
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/* UART */
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#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
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/* Monitor Command Prompt */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_CBSIZE SZ_2K
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* USDHC */
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
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#define CONFIG_SYS_I2C_SPEED 100000
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/* ENET */
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 7
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#define FEC_QUIRK_ENET_MAC
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#define IMX_FEC_BASE 0x30BE0000
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#endif /*_VERDIN_IMX8MM_H */
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