mirror of
https://github.com/AsahiLinux/u-boot
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160e3b38e9
Enable CONFIG_SPI_FLASH_SPANSION in defconfigs of LS1046ARDB and LS1046AQDS which have two spansion flases i.e s25fs512s each of size 64M. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
198 lines
5.7 KiB
C
198 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 Freescale Semiconductor
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* Copyright 2019 NXP
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*/
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#ifndef __LS1046ARDB_H__
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#define __LS1046ARDB_H__
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#include "ls1046a_common.h"
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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/* Physical Memory Map */
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_DDR_SPD
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#define SPD_EEPROM_ADDRESS 0x51
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
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#ifdef CONFIG_EMMC_BOOT
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#define CONFIG_SYS_FSL_PBL_RCW \
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board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
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#else
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
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#endif
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#elif defined(CONFIG_QSPI_BOOT)
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#define CONFIG_SYS_FSL_PBL_RCW \
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board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
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#define CONFIG_SYS_FSL_PBL_PBI \
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board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
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#define CONFIG_SYS_UBOOT_BASE 0x40100000
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#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
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#endif
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#ifndef SPL_NO_IFC
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/* IFC */
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#define CONFIG_FSL_IFC
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/*
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* NAND Flash Definitions
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*/
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#define CONFIG_NAND_FSL_IFC
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#endif
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#define CONFIG_SYS_NAND_BASE 0x7e800000
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_NAND \
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
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| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
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| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
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| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x7) | \
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FTIM0_NAND_TWH(0xa))
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#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0xe) | \
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FTIM1_NAND_TRP(0x18))
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#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
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FTIM2_NAND_TREH(0xa) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CONFIG_SYS_NAND_FTIM3 0x0
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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/*
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* CPLD
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*/
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#define CONFIG_SYS_CPLD_BASE 0x7fb00000
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#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
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#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
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#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
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/* CPLD Timing parameters for IFC GPCM */
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#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
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FTIM0_GPCM_TEADC(0x0e) | \
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FTIM0_GPCM_TEAHC(0x0e))
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#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
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FTIM1_GPCM_TRAD(0x3f))
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#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
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FTIM2_GPCM_TCH(0xf) | \
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FTIM2_GPCM_TWP(0x3E))
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#define CONFIG_SYS_CPLD_FTIM3 0x0
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/* IFC Timing Params */
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
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#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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#define I2C_RETIMER_ADDR 0x18
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/* PMIC */
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#define CONFIG_POWER
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#ifdef CONFIG_POWER
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#define CONFIG_POWER_I2C
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#endif
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/*
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* Environment
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*/
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
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#define AQR105_IRQ_MASK 0x80000000
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/* FMan */
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#ifndef SPL_NO_FMAN
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define RGMII_PHY1_ADDR 0x1
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#define RGMII_PHY2_ADDR 0x2
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#define SGMII_PHY1_ADDR 0x3
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#define SGMII_PHY2_ADDR 0x4
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#define FM1_10GEC1_PHY_ADDR 0x0
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#define FDT_SEQ_MACADDR_FROM_ENV
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#define CONFIG_ETHPRIME "FM1@DTSEC3"
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#endif
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#endif
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#ifndef SPL_NO_MISC
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#undef CONFIG_BOOTCOMMAND
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#ifdef CONFIG_TFABOOT
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#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
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"env exists secureboot && esbc_halt;;"
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#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
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"env exists secureboot && esbc_halt;"
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#else
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#if defined(CONFIG_QSPI_BOOT)
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#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
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"env exists secureboot && esbc_halt;;"
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#elif defined(CONFIG_SD_BOOT)
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#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
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"env exists secureboot && esbc_halt;"
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#endif
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#endif
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#endif
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#include <asm/fsl_secure_boot.h>
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#endif /* __LS1046ARDB_H__ */
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