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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
135 lines
3.1 KiB
C
135 lines
3.1 KiB
C
/*
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* Copyright (C) 2010 Linaro Limited
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* John Rigby <john.rigby@linaro.org>
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*
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* Based on original from Linux kernel source and
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* internal ST-Ericsson U-Boot source.
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* (C) Copyright 2009 Alessandro Rubini
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* (C) Copyright 2010 ST-Ericsson
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* The MTU device has some interrupt control registers
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* followed by 4 timers.
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*/
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/* The timers */
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struct u8500_mtu_timer {
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u32 lr; /* Load value */
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u32 cv; /* Current value */
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u32 cr; /* Control reg */
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u32 bglr; /* ??? */
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};
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/* The MTU that contains the timers */
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struct u8500_mtu {
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u32 imsc; /* Interrupt mask set/clear */
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u32 ris; /* Raw interrupt status */
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u32 mis; /* Masked interrupt status */
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u32 icr; /* Interrupt clear register */
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struct u8500_mtu_timer pt[4];
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};
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/* bits for the control register */
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#define MTU_CR_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR */
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#define MTU_CR_32BITS 0x02
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#define MTU_CR_PRESCALE_1 0x00
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#define MTU_CR_PRESCALE_16 0x04
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#define MTU_CR_PRESCALE_256 0x08
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#define MTU_CR_PRESCALE_MASK 0x0c
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#define MTU_CR_PERIODIC 0x40 /* if 0 = free-running */
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#define MTU_CR_ENA 0x80
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/*
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* The MTU is clocked at 133 MHz by default. (V1 and later)
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*/
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#define TIMER_CLOCK (133 * 1000 * 1000 / 16)
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#define COUNT_TO_USEC(x) ((x) * 16 / 133)
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#define USEC_TO_COUNT(x) ((x) * 133 / 16)
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#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
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#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
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#define TIMER_LOAD_VAL 0xffffffff
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/*
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* MTU timer to use (from 0 to 3).
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*/
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#define MTU_TIMER 2
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static struct u8500_mtu_timer *timer_base =
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&((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER];
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/* macro to read the 32 bit timer: since it decrements, we invert read value */
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#define READ_TIMER() (~readl(&timer_base->cv))
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/* Configure a free-running, auto-wrap counter with /16 prescaler */
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int timer_init(void)
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{
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writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS,
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&timer_base->cr);
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return 0;
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}
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ulong get_timer_masked(void)
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{
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/* current tick value */
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ulong now = TICKS_TO_HZ(READ_TIMER());
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if (now >= gd->arch.lastinc) { /* normal (non rollover) */
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gd->arch.tbl += (now - gd->arch.lastinc);
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} else { /* rollover */
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gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) -
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gd->arch.lastinc) + now;
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}
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gd->arch.lastinc = now;
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return gd->arch.tbl;
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}
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/* Delay x useconds */
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void __udelay(ulong usec)
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{
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long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
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ulong now, last = READ_TIMER();
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while (tmo > 0) {
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now = READ_TIMER();
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if (now > last) /* normal (non rollover) */
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tmo -= now - last;
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else /* rollover */
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tmo -= TIMER_LOAD_VAL - last + now;
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last = now;
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}
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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/*
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* Emulation of Power architecture long long timebase.
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*
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* TODO: Support gd->arch.tbu for real long long timebase.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* Emulation of Power architecture timebase.
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* NB: Low resolution compared to Power tbclk.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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