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25d1936a19
Because of the brackets the & and && is evaluated before the comparison. This is likely not the intention. Change it to test the first and second condition to both be true. cc: Marek Vasut <marex@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
1030 lines
28 KiB
C
1030 lines
28 KiB
C
/*
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* USB HOST XHCI Controller stack
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*
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* Based on xHCI host controller driver in linux-kernel
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* by Sarah Sharp.
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*
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* Copyright (C) 2008 Intel Corp.
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* Author: Sarah Sharp
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*
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* Copyright (C) 2013 Samsung Electronics Co.Ltd
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* Authors: Vivek Gautam <gautam.vivek@samsung.com>
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* Vikas Sajjan <vikas.sajjan@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/**
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* This file gives the xhci stack for usb3.0 looking into
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* xhci specification Rev1.0 (5/21/10).
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* The quirk devices support hasn't been given yet.
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*/
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#include <common.h>
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#include <asm/byteorder.h>
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#include <usb.h>
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#include <malloc.h>
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#include <watchdog.h>
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#include <asm/cache.h>
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#include <asm/unaligned.h>
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#include <asm-generic/errno.h>
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#include "xhci.h"
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#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#endif
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static struct descriptor {
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struct usb_hub_descriptor hub;
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struct usb_device_descriptor device;
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struct usb_config_descriptor config;
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struct usb_interface_descriptor interface;
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struct usb_endpoint_descriptor endpoint;
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struct usb_ss_ep_comp_descriptor ep_companion;
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} __attribute__ ((packed)) descriptor = {
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{
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0xc, /* bDescLength */
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0x2a, /* bDescriptorType: hub descriptor */
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2, /* bNrPorts -- runtime modified */
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cpu_to_le16(0x8), /* wHubCharacteristics */
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10, /* bPwrOn2PwrGood */
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0, /* bHubCntrCurrent */
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{}, /* Device removable */
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{} /* at most 7 ports! XXX */
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},
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{
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0x12, /* bLength */
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1, /* bDescriptorType: UDESC_DEVICE */
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cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
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9, /* bDeviceClass: UDCLASS_HUB */
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0, /* bDeviceSubClass: UDSUBCLASS_HUB */
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3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
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9, /* bMaxPacketSize: 512 bytes 2^9 */
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0x0000, /* idVendor */
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0x0000, /* idProduct */
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cpu_to_le16(0x0100), /* bcdDevice */
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1, /* iManufacturer */
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2, /* iProduct */
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0, /* iSerialNumber */
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1 /* bNumConfigurations: 1 */
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},
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{
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0x9,
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2, /* bDescriptorType: UDESC_CONFIG */
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cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
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1, /* bNumInterface */
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1, /* bConfigurationValue */
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0, /* iConfiguration */
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0x40, /* bmAttributes: UC_SELF_POWER */
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0 /* bMaxPower */
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},
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{
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0x9, /* bLength */
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4, /* bDescriptorType: UDESC_INTERFACE */
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0, /* bInterfaceNumber */
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0, /* bAlternateSetting */
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1, /* bNumEndpoints */
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9, /* bInterfaceClass: UICLASS_HUB */
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0, /* bInterfaceSubClass: UISUBCLASS_HUB */
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0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
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0 /* iInterface */
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},
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{
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0x7, /* bLength */
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5, /* bDescriptorType: UDESC_ENDPOINT */
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0x81, /* bEndpointAddress: IN endpoint 1 */
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3, /* bmAttributes: UE_INTERRUPT */
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8, /* wMaxPacketSize */
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255 /* bInterval */
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},
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{
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0x06, /* ss_bLength */
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0x30, /* ss_bDescriptorType: SS EP Companion */
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0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
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/* ss_bmAttributes: 1 packet per service interval */
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0x00,
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/* ss_wBytesPerInterval: 15 bits for max 15 ports */
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cpu_to_le16(0x02),
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},
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};
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static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
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/**
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* Waits for as per specified amount of time
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* for the "result" to match with "done"
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*
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* @param ptr pointer to the register to be read
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* @param mask mask for the value read
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* @param done value to be campared with result
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* @param usec time to wait till
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* @return 0 if handshake is success else < 0 on failure
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*/
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static int handshake(uint32_t volatile *ptr, uint32_t mask,
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uint32_t done, int usec)
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{
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uint32_t result;
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do {
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result = xhci_readl(ptr);
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if (result == ~(uint32_t)0)
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return -ENODEV;
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result &= mask;
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if (result == done)
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return 0;
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usec--;
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udelay(1);
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} while (usec > 0);
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return -ETIMEDOUT;
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}
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/**
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* Set the run bit and wait for the host to be running.
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*
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* @param hcor pointer to host controller operation registers
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* @return status of the Handshake
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*/
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static int xhci_start(struct xhci_hcor *hcor)
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{
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u32 temp;
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int ret;
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puts("Starting the controller\n");
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temp = xhci_readl(&hcor->or_usbcmd);
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temp |= (CMD_RUN);
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xhci_writel(&hcor->or_usbcmd, temp);
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/*
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* Wait for the HCHalted Status bit to be 0 to indicate the host is
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* running.
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*/
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ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
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if (ret)
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debug("Host took too long to start, "
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"waited %u microseconds.\n",
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XHCI_MAX_HALT_USEC);
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return ret;
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}
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/**
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* Resets the XHCI Controller
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*
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* @param hcor pointer to host controller operation registers
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* @return -EBUSY if XHCI Controller is not halted else status of handshake
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*/
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int xhci_reset(struct xhci_hcor *hcor)
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{
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u32 cmd;
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u32 state;
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int ret;
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/* Halting the Host first */
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debug("// Halt the HC\n");
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state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
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if (!state) {
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cmd = xhci_readl(&hcor->or_usbcmd);
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cmd &= ~CMD_RUN;
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xhci_writel(&hcor->or_usbcmd, cmd);
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}
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ret = handshake(&hcor->or_usbsts,
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STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
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if (ret) {
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printf("Host not halted after %u microseconds.\n",
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XHCI_MAX_HALT_USEC);
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return -EBUSY;
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}
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debug("// Reset the HC\n");
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cmd = xhci_readl(&hcor->or_usbcmd);
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cmd |= CMD_RESET;
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xhci_writel(&hcor->or_usbcmd, cmd);
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ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
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if (ret)
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return ret;
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/*
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* xHCI cannot write to any doorbells or operational registers other
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* than status until the "Controller Not Ready" flag is cleared.
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*/
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return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
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}
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/**
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* Used for passing endpoint bitmasks between the core and HCDs.
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* Find the index for an endpoint given its descriptor.
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* Use the return value to right shift 1 for the bitmask.
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*
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* Index = (epnum * 2) + direction - 1,
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* where direction = 0 for OUT, 1 for IN.
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* For control endpoints, the IN index is used (OUT index is unused), so
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* index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
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*
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* @param desc USB enpdoint Descriptor
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* @return index of the Endpoint
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*/
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static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
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{
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unsigned int index;
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if (usb_endpoint_xfer_control(desc))
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index = (unsigned int)(usb_endpoint_num(desc) * 2);
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else
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index = (unsigned int)((usb_endpoint_num(desc) * 2) -
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(usb_endpoint_dir_in(desc) ? 0 : 1));
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return index;
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}
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/**
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* Issue a configure endpoint command or evaluate context command
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* and wait for it to finish.
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*
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* @param udev pointer to the Device Data Structure
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* @param ctx_change flag to indicate the Context has changed or NOT
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* @return 0 on success, -1 on failure
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*/
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static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
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{
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struct xhci_container_ctx *in_ctx;
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struct xhci_virt_device *virt_dev;
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struct xhci_ctrl *ctrl = udev->controller;
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union xhci_trb *event;
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virt_dev = ctrl->devs[udev->slot_id];
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in_ctx = virt_dev->in_ctx;
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xhci_flush_cache((uint32_t)in_ctx->bytes, in_ctx->size);
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xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
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ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
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event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
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BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
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!= udev->slot_id);
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switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
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case COMP_SUCCESS:
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debug("Successful %s command\n",
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ctx_change ? "Evaluate Context" : "Configure Endpoint");
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break;
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default:
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printf("ERROR: %s command returned completion code %d.\n",
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ctx_change ? "Evaluate Context" : "Configure Endpoint",
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GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
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return -EINVAL;
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}
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xhci_acknowledge_event(ctrl);
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return 0;
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}
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/**
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* Configure the endpoint, programming the device contexts.
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*
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* @param udev pointer to the USB device structure
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* @return returns the status of the xhci_configure_endpoints
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*/
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static int xhci_set_configuration(struct usb_device *udev)
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{
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struct xhci_container_ctx *in_ctx;
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struct xhci_container_ctx *out_ctx;
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struct xhci_input_control_ctx *ctrl_ctx;
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struct xhci_slot_ctx *slot_ctx;
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struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
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int cur_ep;
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int max_ep_flag = 0;
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int ep_index;
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unsigned int dir;
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unsigned int ep_type;
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struct xhci_ctrl *ctrl = udev->controller;
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int num_of_ep;
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int ep_flag = 0;
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u64 trb_64 = 0;
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int slot_id = udev->slot_id;
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struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
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struct usb_interface *ifdesc;
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out_ctx = virt_dev->out_ctx;
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in_ctx = virt_dev->in_ctx;
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num_of_ep = udev->config.if_desc[0].no_of_ep;
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ifdesc = &udev->config.if_desc[0];
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ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
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/* Zero the input context control */
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ctrl_ctx->add_flags = 0;
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ctrl_ctx->drop_flags = 0;
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/* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
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for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
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ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
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ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
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if (max_ep_flag < ep_flag)
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max_ep_flag = ep_flag;
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}
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xhci_inval_cache((uint32_t)out_ctx->bytes, out_ctx->size);
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/* slot context */
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xhci_slot_copy(ctrl, in_ctx, out_ctx);
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slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
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slot_ctx->dev_info &= ~(LAST_CTX_MASK);
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slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
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xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
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/* filling up ep contexts */
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for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
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struct usb_endpoint_descriptor *endpt_desc = NULL;
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endpt_desc = &ifdesc->ep_desc[cur_ep];
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trb_64 = 0;
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ep_index = xhci_get_ep_index(endpt_desc);
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ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
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/* Allocate the ep rings */
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virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
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if (!virt_dev->eps[ep_index].ring)
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return -ENOMEM;
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/*NOTE: ep_desc[0] actually represents EP1 and so on */
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dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
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ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
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ep_ctx[ep_index]->ep_info2 =
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cpu_to_le32(ep_type << EP_TYPE_SHIFT);
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ep_ctx[ep_index]->ep_info2 |=
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cpu_to_le32(MAX_PACKET
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(get_unaligned(&endpt_desc->wMaxPacketSize)));
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ep_ctx[ep_index]->ep_info2 |=
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cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
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((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
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trb_64 = (uintptr_t)
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virt_dev->eps[ep_index].ring->enqueue;
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ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
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virt_dev->eps[ep_index].ring->cycle_state);
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}
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return xhci_configure_endpoints(udev, false);
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}
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/**
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* Issue an Address Device command (which will issue a SetAddress request to
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* the device).
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*
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* @param udev pointer to the Device Data Structure
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* @return 0 if successful else error code on failure
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*/
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static int xhci_address_device(struct usb_device *udev)
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{
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int ret = 0;
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struct xhci_ctrl *ctrl = udev->controller;
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struct xhci_slot_ctx *slot_ctx;
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struct xhci_input_control_ctx *ctrl_ctx;
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struct xhci_virt_device *virt_dev;
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int slot_id = udev->slot_id;
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union xhci_trb *event;
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virt_dev = ctrl->devs[slot_id];
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/*
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* This is the first Set Address since device plug-in
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* so setting up the slot context.
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*/
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debug("Setting up addressable devices\n");
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xhci_setup_addressable_virt_dev(udev);
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ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
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ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
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ctrl_ctx->drop_flags = 0;
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xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
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event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
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BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
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switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
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case COMP_CTX_STATE:
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case COMP_EBADSLT:
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printf("Setup ERROR: address device command for slot %d.\n",
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slot_id);
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ret = -EINVAL;
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break;
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case COMP_TX_ERR:
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puts("Device not responding to set address.\n");
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ret = -EPROTO;
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break;
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case COMP_DEV_ERR:
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puts("ERROR: Incompatible device"
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"for address device command.\n");
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ret = -ENODEV;
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break;
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case COMP_SUCCESS:
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debug("Successful Address Device command\n");
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udev->status = 0;
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break;
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default:
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printf("ERROR: unexpected command completion code 0x%x.\n",
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GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
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ret = -EINVAL;
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break;
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}
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xhci_acknowledge_event(ctrl);
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if (ret < 0)
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/*
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* TODO: Unsuccessful Address Device command shall leave the
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* slot in default state. So, issue Disable Slot command now.
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*/
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return ret;
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xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes,
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virt_dev->out_ctx->size);
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slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
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debug("xHC internal address is: %d\n",
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le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
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return 0;
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}
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|
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/**
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* Issue Enable slot command to the controller to allocate
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* device slot and assign the slot id. It fails if the xHC
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* ran out of device slots, the Enable Slot command timed out,
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* or allocating memory failed.
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*
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* @param udev pointer to the Device Data Structure
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* @return Returns 0 on succes else return error code on failure
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*/
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int usb_alloc_device(struct usb_device *udev)
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{
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union xhci_trb *event;
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struct xhci_ctrl *ctrl = udev->controller;
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int ret;
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/*
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* Root hub will be first device to be initailized.
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* If this device is root-hub, don't do any xHC related
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* stuff.
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*/
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if (ctrl->rootdev == 0) {
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udev->speed = USB_SPEED_SUPER;
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return 0;
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}
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xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
|
|
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
|
|
BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
|
|
!= COMP_SUCCESS);
|
|
|
|
udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
|
|
|
|
xhci_acknowledge_event(ctrl);
|
|
|
|
ret = xhci_alloc_virt_device(udev);
|
|
if (ret < 0) {
|
|
/*
|
|
* TODO: Unsuccessful Address Device command shall leave
|
|
* the slot in default. So, issue Disable Slot command now.
|
|
*/
|
|
puts("Could not allocate xHCI USB device data structures\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Full speed devices may have a max packet size greater than 8 bytes, but the
|
|
* USB core doesn't know that until it reads the first 8 bytes of the
|
|
* descriptor. If the usb_device's max packet size changes after that point,
|
|
* we need to issue an evaluate context command and wait on it.
|
|
*
|
|
* @param udev pointer to the Device Data Structure
|
|
* @return returns the status of the xhci_configure_endpoints
|
|
*/
|
|
int xhci_check_maxpacket(struct usb_device *udev)
|
|
{
|
|
struct xhci_ctrl *ctrl = udev->controller;
|
|
unsigned int slot_id = udev->slot_id;
|
|
int ep_index = 0; /* control endpoint */
|
|
struct xhci_container_ctx *in_ctx;
|
|
struct xhci_container_ctx *out_ctx;
|
|
struct xhci_input_control_ctx *ctrl_ctx;
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
int max_packet_size;
|
|
int hw_max_packet_size;
|
|
int ret = 0;
|
|
struct usb_interface *ifdesc;
|
|
|
|
ifdesc = &udev->config.if_desc[0];
|
|
|
|
out_ctx = ctrl->devs[slot_id]->out_ctx;
|
|
xhci_inval_cache((uint32_t)out_ctx->bytes, out_ctx->size);
|
|
|
|
ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
|
|
hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
|
|
max_packet_size = usb_endpoint_maxp(&ifdesc->ep_desc[0]);
|
|
if (hw_max_packet_size != max_packet_size) {
|
|
debug("Max Packet Size for ep 0 changed.\n");
|
|
debug("Max packet size in usb_device = %d\n", max_packet_size);
|
|
debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
|
|
debug("Issuing evaluate context command.\n");
|
|
|
|
/* Set up the modified control endpoint 0 */
|
|
xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
|
|
ctrl->devs[slot_id]->out_ctx, ep_index);
|
|
in_ctx = ctrl->devs[slot_id]->in_ctx;
|
|
ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
|
|
ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
|
|
ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
|
|
|
|
/*
|
|
* Set up the input context flags for the command
|
|
* FIXME: This won't work if a non-default control endpoint
|
|
* changes max packet sizes.
|
|
*/
|
|
ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
|
|
ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
|
|
ctrl_ctx->drop_flags = 0;
|
|
|
|
ret = xhci_configure_endpoints(udev, true);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* Clears the Change bits of the Port Status Register
|
|
*
|
|
* @param wValue request value
|
|
* @param wIndex request index
|
|
* @param addr address of posrt status register
|
|
* @param port_status state of port status register
|
|
* @return none
|
|
*/
|
|
static void xhci_clear_port_change_bit(u16 wValue,
|
|
u16 wIndex, volatile uint32_t *addr, u32 port_status)
|
|
{
|
|
char *port_change_bit;
|
|
u32 status;
|
|
|
|
switch (wValue) {
|
|
case USB_PORT_FEAT_C_RESET:
|
|
status = PORT_RC;
|
|
port_change_bit = "reset";
|
|
break;
|
|
case USB_PORT_FEAT_C_CONNECTION:
|
|
status = PORT_CSC;
|
|
port_change_bit = "connect";
|
|
break;
|
|
case USB_PORT_FEAT_C_OVER_CURRENT:
|
|
status = PORT_OCC;
|
|
port_change_bit = "over-current";
|
|
break;
|
|
case USB_PORT_FEAT_C_ENABLE:
|
|
status = PORT_PEC;
|
|
port_change_bit = "enable/disable";
|
|
break;
|
|
case USB_PORT_FEAT_C_SUSPEND:
|
|
status = PORT_PLC;
|
|
port_change_bit = "suspend/resume";
|
|
break;
|
|
default:
|
|
/* Should never happen */
|
|
return;
|
|
}
|
|
|
|
/* Change bits are all write 1 to clear */
|
|
xhci_writel(addr, port_status | status);
|
|
|
|
port_status = xhci_readl(addr);
|
|
debug("clear port %s change, actual port %d status = 0x%x\n",
|
|
port_change_bit, wIndex, port_status);
|
|
}
|
|
|
|
/**
|
|
* Save Read Only (RO) bits and save read/write bits where
|
|
* writing a 0 clears the bit and writing a 1 sets the bit (RWS).
|
|
* For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
|
|
*
|
|
* @param state state of the Port Status and Control Regsiter
|
|
* @return a value that would result in the port being in the
|
|
* same state, if the value was written to the port
|
|
* status control register.
|
|
*/
|
|
static u32 xhci_port_state_to_neutral(u32 state)
|
|
{
|
|
/* Save read-only status and port state */
|
|
return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
|
|
}
|
|
|
|
/**
|
|
* Submits the Requests to the XHCI Host Controller
|
|
*
|
|
* @param udev pointer to the USB device structure
|
|
* @param pipe contains the DIR_IN or OUT , devnum
|
|
* @param buffer buffer to be read/written based on the request
|
|
* @return returns 0 if successful else -1 on failure
|
|
*/
|
|
static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
|
|
void *buffer, struct devrequest *req)
|
|
{
|
|
uint8_t tmpbuf[4];
|
|
u16 typeReq;
|
|
void *srcptr = NULL;
|
|
int len, srclen;
|
|
uint32_t reg;
|
|
volatile uint32_t *status_reg;
|
|
struct xhci_ctrl *ctrl = udev->controller;
|
|
struct xhci_hcor *hcor = ctrl->hcor;
|
|
|
|
if ((req->requesttype & USB_RT_PORT) &&
|
|
le16_to_cpu(req->index) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) {
|
|
printf("The request port(%d) is not configured\n",
|
|
le16_to_cpu(req->index) - 1);
|
|
return -EINVAL;
|
|
}
|
|
|
|
status_reg = (volatile uint32_t *)
|
|
(&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
|
|
srclen = 0;
|
|
|
|
typeReq = req->request | req->requesttype << 8;
|
|
|
|
switch (typeReq) {
|
|
case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
|
|
switch (le16_to_cpu(req->value) >> 8) {
|
|
case USB_DT_DEVICE:
|
|
debug("USB_DT_DEVICE request\n");
|
|
srcptr = &descriptor.device;
|
|
srclen = 0x12;
|
|
break;
|
|
case USB_DT_CONFIG:
|
|
debug("USB_DT_CONFIG config\n");
|
|
srcptr = &descriptor.config;
|
|
srclen = 0x19;
|
|
break;
|
|
case USB_DT_STRING:
|
|
debug("USB_DT_STRING config\n");
|
|
switch (le16_to_cpu(req->value) & 0xff) {
|
|
case 0: /* Language */
|
|
srcptr = "\4\3\11\4";
|
|
srclen = 4;
|
|
break;
|
|
case 1: /* Vendor String */
|
|
srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
|
|
srclen = 14;
|
|
break;
|
|
case 2: /* Product Name */
|
|
srcptr = "\52\3X\0H\0C\0I\0 "
|
|
"\0H\0o\0s\0t\0 "
|
|
"\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
|
|
srclen = 42;
|
|
break;
|
|
default:
|
|
printf("unknown value DT_STRING %x\n",
|
|
le16_to_cpu(req->value));
|
|
goto unknown;
|
|
}
|
|
break;
|
|
default:
|
|
printf("unknown value %x\n", le16_to_cpu(req->value));
|
|
goto unknown;
|
|
}
|
|
break;
|
|
case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
|
|
switch (le16_to_cpu(req->value) >> 8) {
|
|
case USB_DT_HUB:
|
|
debug("USB_DT_HUB config\n");
|
|
srcptr = &descriptor.hub;
|
|
srclen = 0x8;
|
|
break;
|
|
default:
|
|
printf("unknown value %x\n", le16_to_cpu(req->value));
|
|
goto unknown;
|
|
}
|
|
break;
|
|
case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
|
|
debug("USB_REQ_SET_ADDRESS\n");
|
|
ctrl->rootdev = le16_to_cpu(req->value);
|
|
break;
|
|
case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
|
|
/* Do nothing */
|
|
break;
|
|
case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
|
|
tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
|
|
tmpbuf[1] = 0;
|
|
srcptr = tmpbuf;
|
|
srclen = 2;
|
|
break;
|
|
case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
|
|
memset(tmpbuf, 0, 4);
|
|
reg = xhci_readl(status_reg);
|
|
if (reg & PORT_CONNECT) {
|
|
tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
|
|
switch (reg & DEV_SPEED_MASK) {
|
|
case XDEV_FS:
|
|
debug("SPEED = FULLSPEED\n");
|
|
break;
|
|
case XDEV_LS:
|
|
debug("SPEED = LOWSPEED\n");
|
|
tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
|
|
break;
|
|
case XDEV_HS:
|
|
debug("SPEED = HIGHSPEED\n");
|
|
tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
|
|
break;
|
|
case XDEV_SS:
|
|
debug("SPEED = SUPERSPEED\n");
|
|
tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
|
|
break;
|
|
}
|
|
}
|
|
if (reg & PORT_PE)
|
|
tmpbuf[0] |= USB_PORT_STAT_ENABLE;
|
|
if ((reg & PORT_PLS_MASK) == XDEV_U3)
|
|
tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
|
|
if (reg & PORT_OC)
|
|
tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
|
|
if (reg & PORT_RESET)
|
|
tmpbuf[0] |= USB_PORT_STAT_RESET;
|
|
if (reg & PORT_POWER)
|
|
/*
|
|
* XXX: This Port power bit (for USB 3.0 hub)
|
|
* we are faking in USB 2.0 hub port status;
|
|
* since there's a change in bit positions in
|
|
* two:
|
|
* USB 2.0 port status PP is at position[8]
|
|
* USB 3.0 port status PP is at position[9]
|
|
* So, we are still keeping it at position [8]
|
|
*/
|
|
tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
|
|
if (reg & PORT_CSC)
|
|
tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
|
|
if (reg & PORT_PEC)
|
|
tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
|
|
if (reg & PORT_OCC)
|
|
tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
|
|
if (reg & PORT_RC)
|
|
tmpbuf[2] |= USB_PORT_STAT_C_RESET;
|
|
|
|
srcptr = tmpbuf;
|
|
srclen = 4;
|
|
break;
|
|
case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
|
|
reg = xhci_readl(status_reg);
|
|
reg = xhci_port_state_to_neutral(reg);
|
|
switch (le16_to_cpu(req->value)) {
|
|
case USB_PORT_FEAT_ENABLE:
|
|
reg |= PORT_PE;
|
|
xhci_writel(status_reg, reg);
|
|
break;
|
|
case USB_PORT_FEAT_POWER:
|
|
reg |= PORT_POWER;
|
|
xhci_writel(status_reg, reg);
|
|
break;
|
|
case USB_PORT_FEAT_RESET:
|
|
reg |= PORT_RESET;
|
|
xhci_writel(status_reg, reg);
|
|
break;
|
|
default:
|
|
printf("unknown feature %x\n", le16_to_cpu(req->value));
|
|
goto unknown;
|
|
}
|
|
break;
|
|
case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
|
|
reg = xhci_readl(status_reg);
|
|
reg = xhci_port_state_to_neutral(reg);
|
|
switch (le16_to_cpu(req->value)) {
|
|
case USB_PORT_FEAT_ENABLE:
|
|
reg &= ~PORT_PE;
|
|
break;
|
|
case USB_PORT_FEAT_POWER:
|
|
reg &= ~PORT_POWER;
|
|
break;
|
|
case USB_PORT_FEAT_C_RESET:
|
|
case USB_PORT_FEAT_C_CONNECTION:
|
|
case USB_PORT_FEAT_C_OVER_CURRENT:
|
|
case USB_PORT_FEAT_C_ENABLE:
|
|
xhci_clear_port_change_bit((le16_to_cpu(req->value)),
|
|
le16_to_cpu(req->index),
|
|
status_reg, reg);
|
|
break;
|
|
default:
|
|
printf("unknown feature %x\n", le16_to_cpu(req->value));
|
|
goto unknown;
|
|
}
|
|
xhci_writel(status_reg, reg);
|
|
break;
|
|
default:
|
|
puts("Unknown request\n");
|
|
goto unknown;
|
|
}
|
|
|
|
debug("scrlen = %d\n req->length = %d\n",
|
|
srclen, le16_to_cpu(req->length));
|
|
|
|
len = min(srclen, le16_to_cpu(req->length));
|
|
|
|
if (srcptr != NULL && len > 0)
|
|
memcpy(buffer, srcptr, len);
|
|
else
|
|
debug("Len is 0\n");
|
|
|
|
udev->act_len = len;
|
|
udev->status = 0;
|
|
|
|
return 0;
|
|
|
|
unknown:
|
|
udev->act_len = 0;
|
|
udev->status = USB_ST_STALLED;
|
|
|
|
return -ENODEV;
|
|
}
|
|
|
|
/**
|
|
* Submits the INT request to XHCI Host cotroller
|
|
*
|
|
* @param udev pointer to the USB device
|
|
* @param pipe contains the DIR_IN or OUT , devnum
|
|
* @param buffer buffer to be read/written based on the request
|
|
* @param length length of the buffer
|
|
* @param interval interval of the interrupt
|
|
* @return 0
|
|
*/
|
|
int
|
|
submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
|
|
int length, int interval)
|
|
{
|
|
/*
|
|
* TODO: Not addressing any interrupt type transfer requests
|
|
* Add support for it later.
|
|
*/
|
|
return -EINVAL;
|
|
}
|
|
|
|
/**
|
|
* submit the BULK type of request to the USB Device
|
|
*
|
|
* @param udev pointer to the USB device
|
|
* @param pipe contains the DIR_IN or OUT , devnum
|
|
* @param buffer buffer to be read/written based on the request
|
|
* @param length length of the buffer
|
|
* @return returns 0 if successful else -1 on failure
|
|
*/
|
|
int
|
|
submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
|
|
int length)
|
|
{
|
|
if (usb_pipetype(pipe) != PIPE_BULK) {
|
|
printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
|
|
return -EINVAL;
|
|
}
|
|
|
|
return xhci_bulk_tx(udev, pipe, length, buffer);
|
|
}
|
|
|
|
/**
|
|
* submit the control type of request to the Root hub/Device based on the devnum
|
|
*
|
|
* @param udev pointer to the USB device
|
|
* @param pipe contains the DIR_IN or OUT , devnum
|
|
* @param buffer buffer to be read/written based on the request
|
|
* @param length length of the buffer
|
|
* @param setup Request type
|
|
* @return returns 0 if successful else -1 on failure
|
|
*/
|
|
int
|
|
submit_control_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
|
|
int length, struct devrequest *setup)
|
|
{
|
|
struct xhci_ctrl *ctrl = udev->controller;
|
|
int ret = 0;
|
|
|
|
if (usb_pipetype(pipe) != PIPE_CONTROL) {
|
|
printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (usb_pipedevice(pipe) == ctrl->rootdev)
|
|
return xhci_submit_root(udev, pipe, buffer, setup);
|
|
|
|
if (setup->request == USB_REQ_SET_ADDRESS)
|
|
return xhci_address_device(udev);
|
|
|
|
if (setup->request == USB_REQ_SET_CONFIGURATION) {
|
|
ret = xhci_set_configuration(udev);
|
|
if (ret) {
|
|
puts("Failed to configure xHCI endpoint\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
|
|
}
|
|
|
|
/**
|
|
* Intialises the XHCI host controller
|
|
* and allocates the necessary data structures
|
|
*
|
|
* @param index index to the host controller data structure
|
|
* @return pointer to the intialised controller
|
|
*/
|
|
int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
|
|
{
|
|
uint32_t val;
|
|
uint32_t val2;
|
|
uint32_t reg;
|
|
struct xhci_hccr *hccr;
|
|
struct xhci_hcor *hcor;
|
|
struct xhci_ctrl *ctrl;
|
|
|
|
if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
|
|
return -ENODEV;
|
|
|
|
if (xhci_reset(hcor) != 0)
|
|
return -ENODEV;
|
|
|
|
ctrl = &xhcic[index];
|
|
|
|
ctrl->hccr = hccr;
|
|
ctrl->hcor = hcor;
|
|
|
|
/*
|
|
* Program the Number of Device Slots Enabled field in the CONFIG
|
|
* register with the max value of slots the HC can handle.
|
|
*/
|
|
val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
|
|
val2 = xhci_readl(&hcor->or_config);
|
|
val |= (val2 & ~HCS_SLOTS_MASK);
|
|
xhci_writel(&hcor->or_config, val);
|
|
|
|
/* initializing xhci data structures */
|
|
if (xhci_mem_init(ctrl, hccr, hcor) < 0)
|
|
return -ENOMEM;
|
|
|
|
reg = xhci_readl(&hccr->cr_hcsparams1);
|
|
descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
|
|
HCS_MAX_PORTS_SHIFT);
|
|
printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
|
|
|
|
/* Port Indicators */
|
|
reg = xhci_readl(&hccr->cr_hccparams);
|
|
if (HCS_INDICATOR(reg))
|
|
put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
|
|
| 0x80, &descriptor.hub.wHubCharacteristics);
|
|
|
|
/* Port Power Control */
|
|
if (HCC_PPC(reg))
|
|
put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
|
|
| 0x01, &descriptor.hub.wHubCharacteristics);
|
|
|
|
if (xhci_start(hcor)) {
|
|
xhci_reset(hcor);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Zero'ing IRQ control register and IRQ pending register */
|
|
xhci_writel(&ctrl->ir_set->irq_control, 0x0);
|
|
xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
|
|
|
|
reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
|
|
printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
|
|
|
|
*controller = &xhcic[index];
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Stops the XHCI host controller
|
|
* and cleans up all the related data structures
|
|
*
|
|
* @param index index to the host controller data structure
|
|
* @return none
|
|
*/
|
|
int usb_lowlevel_stop(int index)
|
|
{
|
|
struct xhci_ctrl *ctrl = (xhcic + index);
|
|
u32 temp;
|
|
|
|
xhci_reset(ctrl->hcor);
|
|
|
|
debug("// Disabling event ring interrupts\n");
|
|
temp = xhci_readl(&ctrl->hcor->or_usbsts);
|
|
xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
|
|
temp = xhci_readl(&ctrl->ir_set->irq_pending);
|
|
xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
|
|
|
|
xhci_hcd_stop(index);
|
|
|
|
xhci_cleanup(ctrl);
|
|
|
|
return 0;
|
|
}
|