mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 06:12:58 +00:00
82 lines
1.5 KiB
C
82 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <fsl_ddr.h>
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#include <fdt_support.h>
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#include <asm/global_data.h>
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#include <linux/libfdt.h>
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#include <env_internal.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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#include <asm/arch-fsl-layerscape/fsl_icid.h>
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#include <i2c.h>
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#include <asm/arch/soc.h>
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#include <fsl_immap.h>
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#include <netdev.h>
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#include <fdtdec.h>
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#include <miiphy.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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fsl_lsch3_early_init_f();
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return 0;
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}
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int board_init(void)
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{
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if (CONFIG_IS_ENABLED(FSL_CAAM))
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sec_init();
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return 0;
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}
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int board_eth_init(struct bd_info *bis)
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{
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return pci_eth_init(bis);
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}
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int checkboard(void)
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{
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printf("EL: %d\n", current_el());
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
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print_ddr_info(0);
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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int nbanks = CONFIG_NR_DRAM_BANKS;
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int node;
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int i;
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ft_cpu_setup(blob, bd);
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/* fixup DT for the two GPP DDR banks */
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for (i = 0; i < nbanks; i++) {
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base[i] = gd->bd->bi_dram[i].start;
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size[i] = gd->bd->bi_dram[i].size;
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}
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fdt_fixup_memory_banks(blob, base, size, nbanks);
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fdt_fixup_icid(blob);
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if (CONFIG_IS_ENABLED(SL28_SPL_LOADS_OPTEE_BL32)) {
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node = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
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if (node)
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fdt_set_node_status(blob, node, FDT_STATUS_OKAY, 0);
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}
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return 0;
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}
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