mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 01:19:49 +00:00
f3285deeca
Since commit [1] A53 u-boot proper is broken.
This is because nodes marked as 'bootph-pre-ram' are
not available at u-boot proper before relocation.
To fix this we mark all nodes in sk-u-boot.dtsi as
'bootph-all'.
Move cbass_mcu node to -r5-sk.dts as it is only required
for R5 SPL.
[1]
9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
105 lines
2.2 KiB
Text
105 lines
2.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
|
*/
|
|
|
|
#include "k3-am642-sk.dts"
|
|
#include "k3-am64-sk-lp4-1600MTs.dtsi"
|
|
#include "k3-am64-ddr.dtsi"
|
|
|
|
#include "k3-am642-sk-u-boot.dtsi"
|
|
|
|
/ {
|
|
aliases {
|
|
remoteproc0 = &sysctrler;
|
|
remoteproc1 = &a53_0;
|
|
};
|
|
|
|
a53_0: a53@0 {
|
|
compatible = "ti,am654-rproc";
|
|
reg = <0x00 0x00a90000 0x00 0x10>;
|
|
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
|
|
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
|
|
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
|
|
resets = <&k3_reset 135 0>;
|
|
clocks = <&k3_clks 61 0>;
|
|
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
|
|
assigned-clock-parents = <&k3_clks 61 2>;
|
|
assigned-clock-rates = <200000000>, <1000000000>;
|
|
ti,sci = <&dmsc>;
|
|
ti,sci-proc-id = <32>;
|
|
ti,sci-host-id = <10>;
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
clk_200mhz: dummy-clock-200mhz {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <200000000>;
|
|
bootph-pre-ram;
|
|
};
|
|
};
|
|
|
|
&cbass_main {
|
|
sysctrler: sysctrler {
|
|
compatible = "ti,am654-system-controller";
|
|
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
|
|
mbox-names = "tx", "rx";
|
|
bootph-pre-ram;
|
|
};
|
|
};
|
|
|
|
&main_esm {
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&cbass_mcu {
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&mcu_esm {
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&dmsc {
|
|
mboxes= <&secure_proxy_main 0>,
|
|
<&secure_proxy_main 1>,
|
|
<&secure_proxy_main 0>;
|
|
mbox-names = "rx", "tx", "notify";
|
|
ti,host-id = <35>;
|
|
ti,secure-host;
|
|
};
|
|
|
|
&sdhci1 {
|
|
clocks = <&clk_200mhz>;
|
|
clock-names = "clk_xin";
|
|
};
|
|
|
|
&serdes_wiz0 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* UART is initialized before SYSFW is started
|
|
* so we can't do any power-domain/clock operations.
|
|
* Delete clock/power-domain properties to avoid
|
|
* UART init failure
|
|
*/
|
|
&main_uart0 {
|
|
/delete-property/ power-domains;
|
|
/delete-property/ clocks;
|
|
/delete-property/ clock-names;
|
|
};
|
|
|
|
/* timer init is called as part of rproc_start() while
|
|
* starting System Firmware, so any clock/power-domain
|
|
* operations will fail as SYSFW is not yet up and running.
|
|
* Delete all clock/power-domain properties to avoid
|
|
* timer init failure.
|
|
* This is an always on timer at 20MHz.
|
|
*/
|
|
&main_timer0 {
|
|
/delete-property/ clocks;
|
|
/delete-property/ assigned-clocks;
|
|
/delete-property/ assigned-clock-parents;
|
|
/delete-property/ power-domains;
|
|
};
|