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5c18384dea
The DRAM controller allows to configure impedance either by using the
calibration against an external high precision 240 ohm resistor, or
by skipping the calibration and loading pre-defined data. The DRAM
controller register guide is available here:
http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_ZQCR0
The new code supports both of the impedance configuration modes:
- If the higher bits of the 'zq' parameter in the 'dram_para' struct
are zero, then the lowest 8 bits are used as the ZPROG value, where
two divisors encoded in lower and higher 4 bits. One divisor is
used for calibrating the termination impedance, and another is used
for the output impedance.
- If bits 27:8 in the 'zq' parameters are non-zero, then they are
used as the pre-defined ZDATA value instead of performing the ZQ
calibration.
Two lowest bits in the 'odt_en' parameter enable ODT for the DQ and DQS
lines individually. Enabling ODT for both DQ and DQS means that the
'odt_en' parameter needs to be set to 3.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| am33xx | ||
| at91 | ||
| bcm281xx | ||
| exynos | ||
| highbank | ||
| keystone | ||
| kona-common | ||
| mx5 | ||
| mx6 | ||
| omap-common | ||
| omap3 | ||
| omap4 | ||
| omap5 | ||
| rmobile | ||
| s5p-common | ||
| s5pc1xx | ||
| socfpga | ||
| sunxi | ||
| tegra-common | ||
| tegra20 | ||
| tegra30 | ||
| tegra114 | ||
| tegra124 | ||
| u8500 | ||
| vf610 | ||
| zynq | ||
| arch_timer.c | ||
| cache_v7.c | ||
| config.mk | ||
| cpu.c | ||
| lowlevel_init.S | ||
| Makefile | ||
| nonsec_virt.S | ||
| psci.S | ||
| start.S | ||
| syslib.c | ||
| virt-dt.c | ||
| virt-v7.c | ||