mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
1221ce459d
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
276 lines
6.3 KiB
C
276 lines
6.3 KiB
C
/*
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* (C) Copyright 2011
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* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
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*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* Copyright 2015 ATS Advanced Telematics Systems GmbH
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* Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
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static const unsigned long io_base[] = {
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STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
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STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
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STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE
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};
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struct stm32_gpio_regs {
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u32 moder; /* GPIO port mode */
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u32 otyper; /* GPIO port output type */
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u32 ospeedr; /* GPIO port output speed */
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u32 pupdr; /* GPIO port pull-up/pull-down */
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u32 idr; /* GPIO port input data */
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u32 odr; /* GPIO port output data */
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u32 bsrr; /* GPIO port bit set/reset */
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u32 lckr; /* GPIO port configuration lock */
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u32 afr[2]; /* GPIO alternate function */
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};
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#define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15)
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#define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \
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x->pupd > 2 || x->speed > 3)
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int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
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const struct stm32_gpio_ctl *ctl)
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{
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struct stm32_gpio_regs *gpio_regs;
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u32 i;
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int rv;
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if (CHECK_DSC(dsc)) {
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rv = -EINVAL;
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goto out;
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}
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if (CHECK_CTL(ctl)) {
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rv = -EINVAL;
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goto out;
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}
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gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
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i = (dsc->pin & 0x07) * 4;
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clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
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i = dsc->pin * 2;
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clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i);
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clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i);
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clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i);
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clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i);
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rv = 0;
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out:
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return rv;
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}
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#elif defined(CONFIG_STM32F1)
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static const unsigned long io_base[] = {
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STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
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STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
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STM32_GPIOG_BASE
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};
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#define STM32_GPIO_CR_MODE_MASK 0x3
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#define STM32_GPIO_CR_MODE_SHIFT(p) (p * 4)
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#define STM32_GPIO_CR_CNF_MASK 0x3
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#define STM32_GPIO_CR_CNF_SHIFT(p) (p * 4 + 2)
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struct stm32_gpio_regs {
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u32 crl; /* GPIO port configuration low */
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u32 crh; /* GPIO port configuration high */
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u32 idr; /* GPIO port input data */
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u32 odr; /* GPIO port output data */
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u32 bsrr; /* GPIO port bit set/reset */
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u32 brr; /* GPIO port bit reset */
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u32 lckr; /* GPIO port configuration lock */
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};
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#define CHECK_DSC(x) (!x || x->port > 6 || x->pin > 15)
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#define CHECK_CTL(x) (!x || x->mode > 3 || x->icnf > 3 || x->ocnf > 3 || \
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x->pupd > 1)
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int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
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const struct stm32_gpio_ctl *ctl)
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{
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struct stm32_gpio_regs *gpio_regs;
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u32 *cr;
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int p, crp;
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int rv;
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if (CHECK_DSC(dsc)) {
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rv = -EINVAL;
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goto out;
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}
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if (CHECK_CTL(ctl)) {
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rv = -EINVAL;
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goto out;
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}
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p = dsc->pin;
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gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
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if (p < 8) {
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cr = &gpio_regs->crl;
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crp = p;
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} else {
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cr = &gpio_regs->crh;
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crp = p - 8;
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}
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clrbits_le32(cr, 0x3 << STM32_GPIO_CR_MODE_SHIFT(crp));
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setbits_le32(cr, ctl->mode << STM32_GPIO_CR_MODE_SHIFT(crp));
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clrbits_le32(cr, 0x3 << STM32_GPIO_CR_CNF_SHIFT(crp));
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/* Inputs set the optional pull up / pull down */
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if (ctl->mode == STM32_GPIO_MODE_IN) {
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setbits_le32(cr, ctl->icnf << STM32_GPIO_CR_CNF_SHIFT(crp));
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clrbits_le32(&gpio_regs->odr, 0x1 << p);
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setbits_le32(&gpio_regs->odr, ctl->pupd << p);
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} else {
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setbits_le32(cr, ctl->ocnf << STM32_GPIO_CR_CNF_SHIFT(crp));
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}
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rv = 0;
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out:
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return rv;
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}
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#else
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#error STM32 family not supported
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#endif
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int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
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{
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struct stm32_gpio_regs *gpio_regs;
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int rv;
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if (CHECK_DSC(dsc)) {
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rv = -EINVAL;
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goto out;
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}
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gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
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if (state)
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writel(1 << dsc->pin, &gpio_regs->bsrr);
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else
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writel(1 << (dsc->pin + 16), &gpio_regs->bsrr);
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rv = 0;
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out:
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return rv;
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}
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int stm32_gpin_get(const struct stm32_gpio_dsc *dsc)
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{
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struct stm32_gpio_regs *gpio_regs;
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int rv;
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if (CHECK_DSC(dsc)) {
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rv = -EINVAL;
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goto out;
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}
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gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
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rv = readl(&gpio_regs->idr) & (1 << dsc->pin);
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out:
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return rv;
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}
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/* Common GPIO API */
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int gpio_request(unsigned gpio, const char *label)
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{
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return 0;
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}
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int gpio_free(unsigned gpio)
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{
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return 0;
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}
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int gpio_direction_input(unsigned gpio)
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{
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struct stm32_gpio_dsc dsc;
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struct stm32_gpio_ctl ctl;
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dsc.port = stm32_gpio_to_port(gpio);
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dsc.pin = stm32_gpio_to_pin(gpio);
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#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
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ctl.af = STM32_GPIO_AF0;
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ctl.mode = STM32_GPIO_MODE_IN;
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ctl.otype = STM32_GPIO_OTYPE_PP;
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ctl.pupd = STM32_GPIO_PUPD_NO;
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ctl.speed = STM32_GPIO_SPEED_50M;
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#elif defined(CONFIG_STM32F1)
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ctl.mode = STM32_GPIO_MODE_IN;
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ctl.icnf = STM32_GPIO_ICNF_IN_FLT;
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ctl.ocnf = STM32_GPIO_OCNF_GP_PP; /* ignored for input */
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ctl.pupd = STM32_GPIO_PUPD_UP; /* ignored for floating */
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#else
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#error STM32 family not supported
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#endif
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return stm32_gpio_config(&dsc, &ctl);
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}
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int gpio_direction_output(unsigned gpio, int value)
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{
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struct stm32_gpio_dsc dsc;
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struct stm32_gpio_ctl ctl;
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int res;
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dsc.port = stm32_gpio_to_port(gpio);
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dsc.pin = stm32_gpio_to_pin(gpio);
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#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
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ctl.af = STM32_GPIO_AF0;
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ctl.mode = STM32_GPIO_MODE_OUT;
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ctl.pupd = STM32_GPIO_PUPD_NO;
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ctl.speed = STM32_GPIO_SPEED_50M;
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#elif defined(CONFIG_STM32F1)
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ctl.mode = STM32_GPIO_MODE_OUT_50M;
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ctl.ocnf = STM32_GPIO_OCNF_GP_PP;
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ctl.icnf = STM32_GPIO_ICNF_IN_FLT; /* ignored for output */
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ctl.pupd = STM32_GPIO_PUPD_UP; /* ignored for output */
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#else
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#error STM32 family not supported
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#endif
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res = stm32_gpio_config(&dsc, &ctl);
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if (res < 0)
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goto out;
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res = stm32_gpout_set(&dsc, value);
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out:
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return res;
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}
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int gpio_get_value(unsigned gpio)
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{
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struct stm32_gpio_dsc dsc;
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dsc.port = stm32_gpio_to_port(gpio);
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dsc.pin = stm32_gpio_to_pin(gpio);
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return stm32_gpin_get(&dsc);
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}
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int gpio_set_value(unsigned gpio, int value)
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{
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struct stm32_gpio_dsc dsc;
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dsc.port = stm32_gpio_to_port(gpio);
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dsc.pin = stm32_gpio_to_pin(gpio);
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return stm32_gpout_set(&dsc, value);
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}
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