mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
4b4159d0f3
There are two revisions of unmatched board with different DDR timing, we'd like to support multi-dtb mechanism in SPL, then it selects the right DTB at runtime according to PCB revision in I2C EEPROM. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
47 lines
1.2 KiB
Text
47 lines
1.2 KiB
Text
CONFIG_RISCV=y
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CONFIG_SPL_GPIO_SUPPORT=y
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CONFIG_SYS_MALLOC_F_LEN=0x3000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_DM_SPI=y
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CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
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CONFIG_SPL_MMC_SUPPORT=y
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CONFIG_SPL=y
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CONFIG_SPL_SPI_SUPPORT=y
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CONFIG_TARGET_SIFIVE_UNMATCHED=y
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CONFIG_ARCH_RV64I=y
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CONFIG_RISCV_SMODE=y
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# CONFIG_SPL_USE_ARCH_MEMMOVE is not set
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
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CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb"
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_SPL_SEPARATE_BSS=y
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CONFIG_SPL_DM_RESET=y
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CONFIG_SPL_YMODEM_SUPPORT=y
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CONFIG_CMD_EEPROM=y
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_PWM=y
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CONFIG_CMD_GPT_RENAME=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_CLK=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_OCORES=y
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CONFIG_E1000=y
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CONFIG_NVME=y
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CONFIG_PCI=y
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CONFIG_PCIE_DW_SIFIVE=y
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CONFIG_DM_RESET=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_PCI=y
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CONFIG_SPL_MULTI_DTB_FIT=y
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CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
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CONFIG_SPL_OF_LIST="hifive-unmatched-a00 hifive-unmatched-a00-rev1"
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CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
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