mirror of
https://github.com/AsahiLinux/u-boot
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7efe195096
Distinguish more clearly between source files meant for producing .dtb from those meant for producing .dtbo. No functional change, as we currently have rules for producing a foo.dtbo from either foo.dts or foo.dtso. Note that in the linux tree, all device tree overlay sources have been renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit 81d362732bac). So this is also a step towards staying closer to linux with respect to both Kbuild and device tree sources. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
85 lines
1.7 KiB
Text
85 lines
1.7 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2021 Linaro
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include "imx8mm-pinfunc.h"
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&ecspi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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fsl,spi-num-chipselects = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&ecspi2 {
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#address-cells = <1>;
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#size-cells = <0>;
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fsl,spi-num-chipselects = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&ecspi3 {
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#address-cells = <1>;
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#size-cells = <0>;
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fsl,spi-num-chipselects = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
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cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
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MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
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MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
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>;
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};
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pinctrl_ecspi1_cs: ecspi1cs {
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fsl,pins = <
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MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000
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>;
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};
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <
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MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x02
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MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x02
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MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x102
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>;
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};
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pinctrl_ecspi2_cs: ecspi2_csgrp {
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fsl,pins = <
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MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000
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>;
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};
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pinctrl_ecspi3: ecspi3grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x02
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MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x02
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MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x102
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>;
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};
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pinctrl_ecspi3_cs: ecspi3_csgrp {
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fsl,pins = <
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MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40000
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>;
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};
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};
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