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https://github.com/AsahiLinux/u-boot
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5b7672fc49
Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
Define MDIO related configs
Added eth.c file
Update t1040.c to support RGMII and SGMII
Update t1040qds.c to support ethernet
Define the PHY address
Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: remove dash from commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
72 lines
2 KiB
C
72 lines
2 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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phy_interface_t fman_port_enet_if(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
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/* handle RGMII first */
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if ((port == FM1_DTSEC2) &&
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((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
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FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) {
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if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
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FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
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return PHY_INTERFACE_MODE_RGMII;
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else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
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FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
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return PHY_INTERFACE_MODE_MII;
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else
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return PHY_INTERFACE_MODE_NONE;
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}
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if ((port == FM1_DTSEC4) &&
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((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
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FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) {
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if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
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FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
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return PHY_INTERFACE_MODE_RGMII;
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else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
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FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
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return PHY_INTERFACE_MODE_MII;
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else
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return PHY_INTERFACE_MODE_NONE;
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}
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if (port == FM1_DTSEC5) {
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if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
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FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)
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return PHY_INTERFACE_MODE_RGMII;
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else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
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FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
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return PHY_INTERFACE_MODE_MII;
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else
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return PHY_INTERFACE_MODE_NONE;
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}
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switch (port) {
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case FM1_DTSEC1:
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case FM1_DTSEC2:
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if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1))
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return PHY_INTERFACE_MODE_QSGMII;
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case FM1_DTSEC3:
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case FM1_DTSEC4:
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case FM1_DTSEC5:
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if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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break;
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default:
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return PHY_INTERFACE_MODE_NONE;
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}
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return PHY_INTERFACE_MODE_NONE;
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}
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