mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 23:33:00 +00:00
54a08c4139
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow"
d5acc10c287e40cc2feeb28710b92e45c93c702c
This patch was created by following steps:
1. Replace all a38x files in U-Boot tree by files from upstream github
Marvell mv-ddr-marvell repository.
2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4:
files=drivers/ddr/marvell/a38x/*
unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \
-UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
-UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \
-UCONFIG_64BIT $files
3. Manually change license to SPDX-License-Identifier
(upstream license in upstream github repository contains long license
texts and U-Boot is using just SPDX-License-Identifier.
After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.
The only change in this patch are:
1. Some fixes with include files.
2. Some function return and basic type defines changes in
mv_ddr_plat.c (to correct Marvell bug).
3. Remove of dead code in newly copied files (as a result of the
filter script stripping out everything other than a38x, dd3, and ddr4).
Reference:
"ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository"
107c3391b9
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
545 lines
17 KiB
C
545 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#if defined(CONFIG_DDR4)
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/* DDR4 Training Database */
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#include "ddr_ml_wrapper.h"
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#include "mv_ddr_topology.h"
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#include "mv_ddr_training_db.h"
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#include "ddr_topology_def.h"
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/* list of allowed frequencies listed in order of enum mv_ddr_freq */
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static unsigned int freq_val[MV_DDR_FREQ_LAST] = {
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130, /* MV_DDR_FREQ_LOW_FREQ */
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650, /* MV_DDR_FREQ_650 */
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666, /* MV_DDR_FREQ_667 */
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800, /* MV_DDR_FREQ_800 */
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933, /* MV_DDR_FREQ_933 */
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1066, /* MV_DDR_FREQ_1066 */
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900, /* MV_DDR_FREQ_900 */
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1000, /* MV_DDR_FREQ_1000 */
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1050, /* MV_DDR_FREQ_1050 */
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1200, /* MV_DDR_FREQ_1200 */
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1333, /* MV_DDR_FREQ_1333 */
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1466, /* MV_DDR_FREQ_1466 */
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1600 /* MV_DDR_FREQ_1600 */
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};
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unsigned int *mv_ddr_freq_tbl_get(void)
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{
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return &freq_val[0];
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}
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u32 mv_ddr_freq_get(enum mv_ddr_freq freq)
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{
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return freq_val[freq];
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}
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/* non-dbi mode - table for cl values per frequency for each speed bin index */
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static struct mv_ddr_cl_val_per_freq cl_table[] = {
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/* 130 650 667 800 933 1067 900 1000 1050 1200 1333 1466 1600 FREQ(MHz)*/
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/* 7.69 1.53 1.5 1.25 1.07 0.937 1.11 1 0.95 0.83 0.75 0.68 0.625 TCK(ns)*/
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{{10, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1600J */
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{{10, 11, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1600K */
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{{10, 12, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1600L */
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{{10, 12, 12, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1866L */
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{{10, 12, 12, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1866M */
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{{10, 12, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1866N */
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{{10, 10, 10, 12, 14, 14, 14, 14, 14, 0, 0, 0, 0} },/* SPEED_BIN_DDR_2133N */
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{{10, 9, 9, 12, 14, 15, 14, 15, 15, 0, 0, 0, 0} },/* SPEED_BIN_DDR_2133P */
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{{10, 10, 10, 12, 14, 16, 14, 16, 16, 0, 0, 0, 0} },/* SPEED_BIN_DDR_2133R */
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{{10, 10, 10, 12, 14, 16, 14, 16, 16, 18, 0, 0, 0} },/* SPEED_BIN_DDR_2400P */
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{{10, 9, 9, 11, 13, 15, 13, 15, 15, 18, 0, 0, 0} },/* SPEED_BIN_DDR_2400R */
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{{10, 9, 9, 11, 13, 15, 13, 15, 15, 17, 0, 0, 0} },/* SPEED_BIN_DDR_2400T */
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{{10, 10, 10, 12, 14, 16, 14, 16, 16, 18, 0, 0, 0} },/* SPEED_BIN_DDR_2400U */
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{{10, 10, 10, 11, 13, 15, 13, 15, 15, 16, 17, 0, 0} },/* SPEED_BIN_DDR_2666T */
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{{10, 9, 10, 11, 13, 15, 13, 15, 15, 17, 18, 0, 0} },/* SPEED_BIN_DDR_2666U */
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{{10, 9, 10, 12, 14, 16, 14, 16, 16, 18, 19, 0, 0} },/* SPEED_BIN_DDR_2666V */
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{{10, 10, 10, 12, 14, 16, 14, 16, 16, 18, 20, 0, 0} },/* SPEED_BIN_DDR_2666W */
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{{10, 10, 9, 11, 13, 15, 13, 15, 15, 16, 18, 19, 0} },/* SPEED_BIN_DDR_2933V */
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{{10, 9, 10, 11, 13, 15, 13, 15, 15, 17, 19, 20, 0} },/* SPEED_BIN_DDR_2933W */
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{{10, 9, 10, 12, 14, 16, 14, 16, 16, 18, 20, 21, 0} },/* SPEED_BIN_DDR_2933Y */
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{{10, 10, 10, 12, 14, 16, 14, 16, 16, 18, 20, 22, 0} },/* SPEED_BIN_DDR_2933AA*/
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{{10, 10, 9, 11, 13, 15, 13, 15, 15, 16, 18, 20, 20} },/* SPEED_BIN_DDR_3200W */
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{{10, 9, 0, 11, 13, 15, 13, 15, 15, 17, 19, 22, 22} },/* SPEED_BIN_DDR_3200AA*/
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{{10, 9, 10, 12, 14, 16, 14, 16, 16, 18, 20, 24, 24} } /* SPEED_BIN_DDR_3200AC*/
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};
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u32 mv_ddr_cl_val_get(u32 index, u32 freq)
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{
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return cl_table[index].cl_val[freq];
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}
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/* dbi mode - table for cl values per frequency for each speed bin index */
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struct mv_ddr_cl_val_per_freq cas_latency_table_dbi[] = {
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/* 130 650 667 800 933 1067 900 1000 1050 1200 1333 1466 1600 FREQ(MHz)*/
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/* 7.69 1.53 1.5 1.25 1.07 0.937 1.11 1 0.95 0.83 0.75 0.68 0.625 TCK(ns)*/
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{{0, 12, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1600J */
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{{0, 13, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1600K */
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{{0, 14, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1600L */
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{{0, 14, 14, 14, 0, 0, 14, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1866L */
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{{0, 14, 14, 15, 0, 0, 15, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1866M */
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{{0, 14, 14, 16, 0, 0, 16, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1866N */
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{{0, 12, 12, 14, 16, 17, 14, 17, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_2133N */
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{{0, 11, 11, 14, 16, 18, 14, 18, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_2133P */
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{{0, 12, 12, 14, 16, 19, 14, 19, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_2133R */
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{{0, 12, 12, 14, 16, 19, 14, 19, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_2400P */
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{{0, 11, 11, 13, 15, 18, 13, 18, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_2400R */
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{{0, 11, 11, 13, 15, 18, 13, 18, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_2400T */
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{{0, 12, 12, 14, 16, 19, 14, 19, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_2400U */
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{{10, 10, 11, 13, 15, 18, 13, 18, 18, 19, 20, 0, 0} },/* SPEED_BIN_DDR_2666T */
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{{10, 9, 11, 13, 15, 18, 13, 18, 18, 20, 21, 0, 0} },/* SPEED_BIN_DDR_2666U */
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{{10, 9, 12, 14, 16, 19, 14, 19, 19, 21, 22, 0, 0} },/* SPEED_BIN_DDR_2666V */
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{{10, 10, 12, 14, 16, 19, 14, 19, 19, 21, 23, 0, 0} },/* SPEED_BIN_DDR_2666W */
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{{10, 10, 11, 13, 15, 18, 15, 18, 18, 19, 21, 23, 0} },/* SPEED_BIN_DDR_2933V */
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{{10, 9, 12, 13, 15, 18, 15, 18, 18, 20, 22, 24, 0} },/* SPEED_BIN_DDR_2933W */
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{{10, 9, 12, 14, 16, 19, 16, 19, 19, 21, 23, 26, 0} },/* SPEED_BIN_DDR_2933Y */
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{{10, 10, 12, 14, 16, 19, 16, 19, 19, 21, 23, 26, 0} },/* SPEED_BIN_DDR_2933AA*/
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{{10, 10, 11, 13, 15, 18, 15, 18, 18, 19, 21, 24, 24} },/* SPEED_BIN_DDR_3200W */
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{{10, 9, 0, 13, 15, 18, 15, 18, 18, 20, 22, 26, 26} },/* SPEED_BIN_DDR_3200AA*/
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{{10, 9, 12, 14, 16, 19, 16, 19, 19, 21, 23, 28, 28} } /* SPEED_BIN_DDR_3200AC*/
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};
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/* table for cwl values per speed bin index */
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static struct mv_ddr_cl_val_per_freq cwl_table[] = {
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/* 130 650 667 800 933 1067 900 1000 1050 1200 1333 1466 1600 FREQ(MHz)*/
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/* 7.69 1.53 1.5 1.25 1.07 0.937 1.11 1 0.95 0.83 0.75 0.68 0.625 TCK(ns)*/
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{{9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1600J */
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{{9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1600K */
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{{9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1600L */
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{{9, 9, 9, 10, 0, 0, 10, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1866L */
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{{9, 9, 9, 10, 0, 0, 10, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1866M */
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{{9, 9, 9, 10, 0, 0, 10, 0, 0, 0, 0, 0, 0} },/* SPEED_BIN_DDR_1866N */
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{{9, 9, 9, 9, 10, 11, 10, 11, 10, 11, 0, 0, 0} },/* SPEED_BIN_DDR_2133N */
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{{9, 9, 9, 9, 10, 11, 10, 11, 10, 11, 0, 0, 0} },/* SPEED_BIN_DDR_2133P */
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{{9, 9, 9, 10, 10, 11, 10, 11, 10, 11, 0, 0, 0} },/* SPEED_BIN_DDR_2133R */
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{{9, 9, 9, 9, 10, 11, 10, 11, 10, 12, 0, 0, 0} },/* SPEED_BIN_DDR_2400P */
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{{9, 9, 9, 9, 10, 11, 10, 11, 10, 12, 0, 0, 0} },/* SPEED_BIN_DDR_2400R */
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{{9, 9, 9, 9, 10, 11, 10, 11, 10, 12, 0, 0, 0} },/* SPEED_BIN_DDR_2400T */
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{{9, 9, 9, 9, 10, 11, 10, 11, 10, 12, 0, 0, 0} },/* SPEED_BIN_DDR_2400U */
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{{10, 10, 9, 9, 10, 11, 10, 11, 11, 12, 14, 0, 0} },/* SPEED_BIN_DDR_2666T */
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{{10, 9, 9, 9, 10, 11, 10, 11, 11, 12, 14, 0, 0} },/* SPEED_BIN_DDR_2666U */
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{{10, 9, 9, 9, 10, 11, 10, 11, 11, 12, 14, 0, 0} },/* SPEED_BIN_DDR_2666V */
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{{10, 10, 9, 9, 10, 11, 10, 11, 11, 12, 14, 0, 0} },/* SPEED_BIN_DDR_2666W */
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{{10, 10, 9, 9, 10, 11, 10, 11, 11, 12, 14, 16, 0} },/* SPEED_BIN_DDR_2933V */
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{{10, 9, 9, 9, 10, 11, 10, 11, 11, 12, 14, 16, 0} },/* SPEED_BIN_DDR_2933W */
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{{10, 9, 9, 9, 10, 11, 10, 11, 11, 12, 14, 16, 0} },/* SPEED_BIN_DDR_2933Y */
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{{10, 10, 9, 9, 10, 11, 10, 11, 11, 12, 14, 16, 0} },/* SPEED_BIN_DDR_2933AA*/
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{{10, 10, 9, 9, 10, 11, 10, 11, 11, 12, 14, 16, 16} },/* SPEED_BIN_DDR_3200W */
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{{10, 9, 9, 9, 10, 11, 10, 11, 11, 12, 14, 16, 16} },/* SPEED_BIN_DDR_3200AA*/
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{{10, 9, 9, 9, 10, 11, 10, 11, 11, 12, 14, 16, 16} } /* SPEED_BIN_DDR_3200AC*/
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};
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u32 mv_ddr_cwl_val_get(u32 index, u32 freq)
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{
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return cwl_table[index].cl_val[freq];
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}
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/*
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* rfc values, ns
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* note: values per JEDEC speed bin 1866; TODO: check it
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*/
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static unsigned int rfc_table[] = {
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0, /* placholder */
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0, /* placholder */
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160, /* 2G */
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260, /* 4G */
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350, /* 8G */
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0, /* TODO: placeholder for 16-Mbit die capacity */
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0, /* TODO: placeholder for 32-Mbit die capacity*/
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0, /* TODO: placeholder for 12-Mbit die capacity */
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0 /* TODO: placeholder for 24-Mbit die capacity */
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};
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u32 mv_ddr_rfc_get(u32 mem)
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{
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return rfc_table[mem];
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}
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u16 rtt_table[] = {
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0xffff,
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60,
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120,
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40,
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240,
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48,
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80,
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34
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};
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u8 twr_mask_table[] = {
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0xa,
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0xa,
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0xa,
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0xa,
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0xa,
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0xa,
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0xa,
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0xa,
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0xa,
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0xa,
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0x0, /* 10 */
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0xa,
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0x1, /* 12 */
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0xa,
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0x2, /* 14 */
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0xa,
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0x3, /* 16 */
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0xa,
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0x4, /* 18 */
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0xa,
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0x5, /* 20 */
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0xa,
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0xa, /* 22 */
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0xa,
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0x6 /* 24 */
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};
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u8 cl_mask_table[] = {
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x1, /* 10 */
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0x2,
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0x3, /* 12 */
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0x4,
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0x5, /* 14 */
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0x6,
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0x7, /* 16 */
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0xd,
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0x8, /* 18 */
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0x0,
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0x9, /* 20 */
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0x0,
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0xa, /* 22 */
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0x0,
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0xb /* 24 */
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};
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u8 cwl_mask_table[] = {
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x1, /* 10 */
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0x2,
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0x3, /* 12 */
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0x0,
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0x4, /* 14 */
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0x0,
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0x5, /* 16 */
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0x0,
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0x6 /* 18 */
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};
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u32 speed_bin_table_t_rcd_t_rp[] = {
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12500,
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13750,
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15000,
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12850,
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13920,
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15000,
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13130,
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14060,
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15000,
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12500,
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13320,
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14160,
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15000,
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12750,
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13500,
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14250,
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15000,
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12960,
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13640,
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14320,
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15000,
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12500,
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13750,
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15000
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};
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u32 speed_bin_table_t_rc[] = {
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47500,
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48750,
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50000,
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46850,
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47920,
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49000,
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46130,
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47060,
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48000,
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44500,
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45320,
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46160,
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47000,
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44750,
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45500,
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46250,
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47000,
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44960,
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45640,
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46320,
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47000,
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44500,
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45750,
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47000
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};
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static struct mv_ddr_page_element page_tbl[] = {
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/* 8-bit, 16-bit page size */
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{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 512M */
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{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 1G */
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{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 2G */
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{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 4G */
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{MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 8G */
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{0, 0}, /* TODO: placeholder for 16-Mbit die capacity */
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{0, 0}, /* TODO: placeholder for 32-Mbit die capacity */
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{0, 0}, /* TODO: placeholder for 12-Mbit die capacity */
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{0, 0} /* TODO: placeholder for 24-Mbit die capacity */
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};
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u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size)
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{
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if (bus_width == MV_DDR_DEV_WIDTH_8BIT)
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return page_tbl[mem_size].page_size_8bit;
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else
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return page_tbl[mem_size].page_size_16bit;
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}
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/* DLL locking time, tDLLK */
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#define MV_DDR_TDLLK_DDR4_1600 597
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#define MV_DDR_TDLLK_DDR4_1866 597
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#define MV_DDR_TDLLK_DDR4_2133 768
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#define MV_DDR_TDLLK_DDR4_2400 768
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#define MV_DDR_TDLLK_DDR4_2666 854
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#define MV_DDR_TDLLK_DDR4_2933 940
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#define MV_DDR_TDLLK_DDR4_3200 1024
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static int mv_ddr_tdllk_get(unsigned int freq, unsigned int *tdllk)
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{
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if (freq >= 1600)
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*tdllk = MV_DDR_TDLLK_DDR4_3200;
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else if (freq >= 1466)
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*tdllk = MV_DDR_TDLLK_DDR4_2933;
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else if (freq >= 1333)
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*tdllk = MV_DDR_TDLLK_DDR4_2666;
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else if (freq >= 1200)
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*tdllk = MV_DDR_TDLLK_DDR4_2400;
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else if (freq >= 1066)
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*tdllk = MV_DDR_TDLLK_DDR4_2133;
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else if (freq >= 933)
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*tdllk = MV_DDR_TDLLK_DDR4_1866;
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else if (freq >= 800)
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*tdllk = MV_DDR_TDLLK_DDR4_1600;
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else {
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printf("error: %s: unsupported data rate found\n", __func__);
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return -1;
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}
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return 0;
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}
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/* return speed bin value for selected index and element */
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unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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unsigned int freq;
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u32 result = 0;
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/* get frequency in MHz */
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freq = mv_ddr_freq_get(tm->interface_params[0].memory_freq);
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switch (element) {
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case SPEED_BIN_TRCD:
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case SPEED_BIN_TRP:
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if (tm->cfg_src == MV_DDR_CFG_SPD)
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result = tm->timing_data[MV_DDR_TRCD_MIN];
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else
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result = speed_bin_table_t_rcd_t_rp[index];
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break;
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case SPEED_BIN_TRAS:
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if (tm->cfg_src == MV_DDR_CFG_SPD)
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result = tm->timing_data[MV_DDR_TRAS_MIN];
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else {
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if (index <= SPEED_BIN_DDR_1600L)
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result = 35000;
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else if (index <= SPEED_BIN_DDR_1866N)
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result = 34000;
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else if (index <= SPEED_BIN_DDR_2133R)
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result = 33000;
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else
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result = 32000;
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}
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break;
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case SPEED_BIN_TRC:
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if (tm->cfg_src == MV_DDR_CFG_SPD)
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result = tm->timing_data[MV_DDR_TRC_MIN];
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else
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result = speed_bin_table_t_rc[index];
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break;
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case SPEED_BIN_TRRD0_5K:
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case SPEED_BIN_TRRD1K:
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if (tm->cfg_src == MV_DDR_CFG_SPD)
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result = tm->timing_data[MV_DDR_TRRD_S_MIN];
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else {
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if (index <= SPEED_BIN_DDR_1600L)
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result = 5000;
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else if (index <= SPEED_BIN_DDR_1866N)
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result = 4200;
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else if (index <= SPEED_BIN_DDR_2133R)
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result = 3700;
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else if (index <= SPEED_BIN_DDR_2400U)
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result = 3500;
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else if (index <= SPEED_BIN_DDR_2666W)
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result = 3000;
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else if (index <= SPEED_BIN_DDR_2933AA)
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result = 2700;
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else
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result = 2500;
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}
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break;
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case SPEED_BIN_TRRD2K:
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if (tm->cfg_src == MV_DDR_CFG_SPD)
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result = tm->timing_data[MV_DDR_TRRD_S_MIN];
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else {
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if (index <= SPEED_BIN_DDR_1600L)
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result = 6000;
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else
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result = 5300;
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}
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break;
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case SPEED_BIN_TRRDL0_5K:
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case SPEED_BIN_TRRDL1K:
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if (tm->cfg_src == MV_DDR_CFG_SPD)
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result = tm->timing_data[MV_DDR_TRRD_L_MIN];
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else {
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if (index <= SPEED_BIN_DDR_1600L)
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result = 6000;
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else if (index <= SPEED_BIN_DDR_2133R)
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result = 5300;
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else
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result = 4900;
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}
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break;
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case SPEED_BIN_TRRDL2K:
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if (tm->cfg_src == MV_DDR_CFG_SPD)
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result = tm->timing_data[MV_DDR_TRRD_L_MIN];
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else {
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if (index <= SPEED_BIN_DDR_1600L)
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result = 7500;
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else
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result = 6400;
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}
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break;
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case SPEED_BIN_TPD:
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result = 5000;
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break;
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case SPEED_BIN_TFAW0_5K:
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if (tm->cfg_src == MV_DDR_CFG_SPD)
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result = tm->timing_data[MV_DDR_TFAW_MIN];
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else {
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if (index <= SPEED_BIN_DDR_1600L)
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result = 20000;
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else if (index <= SPEED_BIN_DDR_1866N)
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result = 17000;
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else if (index <= SPEED_BIN_DDR_2133R)
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result = 15000;
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else if (index <= SPEED_BIN_DDR_2400U)
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result = 13000;
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else if (index <= SPEED_BIN_DDR_2666W)
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result = 12000;
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else if (index <= SPEED_BIN_DDR_2933AA)
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result = 10875;
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else
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result = 10000;
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}
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break;
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case SPEED_BIN_TFAW1K:
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if (tm->cfg_src == MV_DDR_CFG_SPD)
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result = tm->timing_data[MV_DDR_TFAW_MIN];
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else {
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if (index <= SPEED_BIN_DDR_1600L)
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result = 25000;
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else if (index <= SPEED_BIN_DDR_1866N)
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result = 23000;
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else
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result = 21000;
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}
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break;
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case SPEED_BIN_TFAW2K:
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if (tm->cfg_src == MV_DDR_CFG_SPD)
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result = tm->timing_data[MV_DDR_TFAW_MIN];
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else {
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if (index <= SPEED_BIN_DDR_1600L)
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result = 35000;
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else
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result = 30000;
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}
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break;
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case SPEED_BIN_TWTR:
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result = 2500;
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/* FIXME: wa: set twtr_s to a default value, if it's unset on spd */
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if (tm->cfg_src == MV_DDR_CFG_SPD && tm->timing_data[MV_DDR_TWTR_S_MIN])
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result = tm->timing_data[MV_DDR_TWTR_S_MIN];
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break;
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case SPEED_BIN_TWTRL:
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case SPEED_BIN_TRTP:
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result = 7500;
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/* FIXME: wa: set twtr_l to a default value, if it's unset on spd */
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if (tm->cfg_src == MV_DDR_CFG_SPD && tm->timing_data[MV_DDR_TWTR_L_MIN])
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result = tm->timing_data[MV_DDR_TWTR_L_MIN];
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break;
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case SPEED_BIN_TWR:
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case SPEED_BIN_TMOD:
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result = 15000;
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/* FIXME: wa: set twr to a default value, if it's unset on spd */
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if (tm->cfg_src == MV_DDR_CFG_SPD && tm->timing_data[MV_DDR_TWR_MIN])
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result = tm->timing_data[MV_DDR_TWR_MIN];
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break;
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case SPEED_BIN_TXPDLL:
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result = 24000;
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break;
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case SPEED_BIN_TXSDLL:
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if (mv_ddr_tdllk_get(freq, &result))
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result = 0;
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break;
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case SPEED_BIN_TCCDL:
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if (tm->cfg_src == MV_DDR_CFG_SPD)
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result = tm->timing_data[MV_DDR_TCCD_L_MIN];
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else {
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if (index <= SPEED_BIN_DDR_1600L)
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result = 6250;
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else if (index <= SPEED_BIN_DDR_2133R)
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result = 5355;
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else
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result = 5000;
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}
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break;
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default:
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printf("error: %s: invalid element [%d] found\n", __func__, (int)element);
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break;
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}
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return result;
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}
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#endif /* CONFIG_DDR4 */
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