u-boot/drivers/ddr/marvell/a38x/ddr3_logging_def.h
Tony Dinh 54a08c4139 ddr: marvell: a38x: Add support for DDR4 from Marvell mv-ddr-marvell repository
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git

up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow"
d5acc10c287e40cc2feeb28710b92e45c93c702c

This patch was created by following steps:

	1. Replace all a38x files in U-Boot tree by files from upstream github
	Marvell mv-ddr-marvell repository.

	2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4:

	files=drivers/ddr/marvell/a38x/*
	unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \
		-UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
		-UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
		-UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \
		-UCONFIG_64BIT $files

	3. Manually change license to SPDX-License-Identifier
	(upstream license in  upstream github repository contains long license
	texts and U-Boot is using just SPDX-License-Identifier.

After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.

The only change in this patch are:
	1. Some fixes with include files.
	2. Some function return and basic type defines changes in
	mv_ddr_plat.c (to correct Marvell bug).
	3. Remove of dead code in newly copied files (as a result of the
	filter script stripping out everything other than a38x, dd3, and ddr4).

Reference:
    "ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository"
    107c3391b9

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-01-26 07:30:20 +01:00

131 lines
3.5 KiB
C

/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*/
#ifndef _DDR3_LOGGING_CONFIG_H
#define _DDR3_LOGGING_CONFIG_H
#ifdef SILENT_LIB
#define DEBUG_TRAINING_BIST_ENGINE(level, s)
#define DEBUG_TRAINING_IP(level, s)
#define DEBUG_CENTRALIZATION_ENGINE(level, s)
#define DEBUG_TRAINING_HW_ALG(level, s)
#define DEBUG_TRAINING_IP_ENGINE(level, s)
#define DEBUG_LEVELING(level, s)
#define DEBUG_PBS_ENGINE(level, s)
#define DEBUG_TRAINING_STATIC_IP(level, s)
#define DEBUG_TRAINING_ACCESS(level, s)
#else
#ifdef LIB_FUNCTIONAL_DEBUG_ONLY
#define DEBUG_TRAINING_BIST_ENGINE(level, s)
#define DEBUG_TRAINING_IP_ENGINE(level, s)
#define DEBUG_TRAINING_IP(level, s) \
if (level >= debug_training) \
printf s
#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
if (level >= debug_centralization) \
printf s
#define DEBUG_TRAINING_HW_ALG(level, s) \
if (level >= debug_training_hw_alg) \
printf s
#define DEBUG_LEVELING(level, s) \
if (level >= debug_leveling) \
printf s
#define DEBUG_PBS_ENGINE(level, s) \
if (level >= debug_pbs) \
printf s
#define DEBUG_TRAINING_STATIC_IP(level, s) \
if (level >= debug_training_static) \
printf s
#define DEBUG_TRAINING_ACCESS(level, s) \
if (level >= debug_training_access) \
printf s
#else
#define DEBUG_TRAINING_BIST_ENGINE(level, s) \
if (level >= debug_training_bist) \
printf s
#define DEBUG_TRAINING_IP_ENGINE(level, s) \
if (level >= debug_training_ip) \
printf s
#define DEBUG_TRAINING_IP(level, s) \
if (level >= debug_training) \
printf s
#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
if (level >= debug_centralization) \
printf s
#define DEBUG_TRAINING_HW_ALG(level, s) \
if (level >= debug_training_hw_alg) \
printf s
#define DEBUG_LEVELING(level, s) \
if (level >= debug_leveling) \
printf s
#define DEBUG_PBS_ENGINE(level, s) \
if (level >= debug_pbs) \
printf s
#define DEBUG_TRAINING_STATIC_IP(level, s) \
if (level >= debug_training_static) \
printf s
#define DEBUG_TRAINING_ACCESS(level, s) \
if (level >= debug_training_access) \
printf s
#endif
#endif
#ifdef CONFIG_DDR4
#ifdef SILENT_LIB
#define DEBUG_TAP_TUNING_ENGINE(level, s)
#define DEBUG_CALIBRATION(level, s)
#define DEBUG_DDR4_CENTRALIZATION(level, s)
#define DEBUG_DM_TUNING(level, s)
#else /* SILENT_LIB */
#define DEBUG_TAP_TUNING_ENGINE(level, s) \
if (level >= debug_tap_tuning) \
printf s
#define DEBUG_CALIBRATION(level, s) \
if (level >= debug_calibration) \
printf s
#define DEBUG_DDR4_CENTRALIZATION(level, s) \
if (level >= debug_ddr4_centralization) \
printf s
#define DEBUG_DM_TUNING(level, s) \
if (level >= debug_dm_tuning) \
printf s
#endif /* SILENT_LIB */
#endif /* CONFIG_DDR4 */
/* Logging defines */
enum mv_ddr_debug_level {
DEBUG_LEVEL_TRACE = 1,
DEBUG_LEVEL_INFO = 2,
DEBUG_LEVEL_ERROR = 3,
DEBUG_LEVEL_LAST
};
enum ddr_lib_debug_block {
DEBUG_BLOCK_STATIC,
DEBUG_BLOCK_TRAINING_MAIN,
DEBUG_BLOCK_LEVELING,
DEBUG_BLOCK_CENTRALIZATION,
DEBUG_BLOCK_PBS,
DEBUG_BLOCK_IP,
DEBUG_BLOCK_BIST,
DEBUG_BLOCK_ALG,
DEBUG_BLOCK_DEVICE,
DEBUG_BLOCK_ACCESS,
DEBUG_STAGES_REG_DUMP,
#if defined(CONFIG_DDR4)
DEBUG_TAP_TUNING_ENGINE,
DEBUG_BLOCK_CALIBRATION,
DEBUG_BLOCK_DDR4_CENTRALIZATION,
DEBUG_DM_TUNING,
#endif /* CONFIG_DDR4 */
/* All excluding IP and REG_DUMP, should be enabled separatelly */
DEBUG_BLOCK_ALL
};
int ddr3_tip_print_log(u32 dev_num, u32 mem_addr);
int ddr3_tip_print_stability_log(u32 dev_num);
#endif /* _DDR3_LOGGING_CONFIG_H */