mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-18 01:03:05 +00:00
39dca76c34
Due to an upstream change, the ls1028a.dtsi bindings for the mscc_felix
switch got accepted with all ports disabled by default and with no link
to the DSA master - this needs to be done on a per board basis.
Note that enetc-2 is not currently disabled in the ls1028a.dtsi, but
presumably at some point it might become. Explicitly enable it in the
QDS device trees anyway, to proactively avoid issues when that happens.
Fixes: a7fdac7e2a ("arm: dts: ls1028a: define QDS networking protocol combinations")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
72 lines
1.7 KiB
Text
72 lines
1.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* NXP LS1028A-QDS device tree fragment for RCW 9999
|
|
*
|
|
* Copyright 2019-2021 NXP Semiconductors
|
|
*/
|
|
|
|
/*
|
|
* This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY.
|
|
* LS1028A QDS boards with lane B rework require two cards for the 4 switch
|
|
* ports, QDS boards without the lane B rework only require one card.
|
|
*
|
|
* Switch ports are routed as follows:
|
|
* Port 0 goes to 1st port of VSC8234 quad card in slot 1,
|
|
* Port 1:
|
|
* - if the QDS has had lane B rework, it is 1st port in slot 2,
|
|
* - otherwise it is 2nd port in slot 1.
|
|
* Port 2:
|
|
* - if DIP SW5[1] = 0 it is 3rd port in slot 1,
|
|
* - otherwise it is 1st port in slot 3.
|
|
* Port 3:
|
|
* - if DIP SW5[2-3] = 00b it is 4th port in slot 1,
|
|
* - if DIP SW5[2-3] = 01b it is 2nd port in slot 3,
|
|
* - if DIP SW5[2-3] = 11b it is 1st port in slot 4.
|
|
*
|
|
* The following DTS assumes QDS lane B rework and DIP SW5[1-3] = 000b. Two
|
|
* SCH-24801 cards are required in slots 1 and 2.
|
|
*/
|
|
&slot1 {
|
|
#include "fsl-sch-24801.dtsi"
|
|
};
|
|
|
|
&slot2 {
|
|
#include "fsl-sch-24801.dtsi"
|
|
};
|
|
|
|
&enetc2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&mscc_felix {
|
|
status = "okay";
|
|
};
|
|
|
|
&mscc_felix_port0 {
|
|
status = "okay";
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
|
|
};
|
|
|
|
&mscc_felix_port1 {
|
|
status = "okay";
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
|
|
};
|
|
|
|
&mscc_felix_port2 {
|
|
status = "okay";
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
|
|
};
|
|
|
|
&mscc_felix_port3 {
|
|
status = "okay";
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
|
|
};
|
|
|
|
&mscc_felix_port4 {
|
|
ethernet = <&enetc2>;
|
|
status = "okay";
|
|
};
|