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https://github.com/AsahiLinux/u-boot
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c350601348
With commit 8678776df6 (arm: mvebu: armada-3720-uDPU: fix PHY mode
definition to sgmii-2500) the PHY mode was switch to "sgmii-2500", even
when this is functionally incorrect since "2500base-x" was not supported
in U-Boot at that time. As this mode is now supported (at least present
in the headers), this patch moves back to the orinal version.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Cc: Vladimir Vid <vladimir.vid@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
195 lines
3.7 KiB
Text
195 lines
3.7 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device tree for the uDPU board.
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* Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
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* Copyright (C) 2016 Marvell
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* Copyright (C) 2018 Methode
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* Copyright (C) 2018 Telus
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*
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* Vladimir Vid <vladimir.vid@sartura.hr>
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*/
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/dts-v1/;
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#include "armada-37xx.dtsi"
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#include "armada-3720-uDPU-u-boot.dtsi"
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/ {
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model = "Methode uDPU Board";
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compatible = "methode,udpu";
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs = "console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000";
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};
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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spi0 = &spi0;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
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};
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mdio: mdio@32004 {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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scsi: scsi {
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compatible = "marvell,mvebu-scsi";
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#address-cells = <1>;
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#size-cells = <1>;
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max-id = <1>;
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max-lun = <1>;
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status = "okay";
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};
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i2c1: i2c@11080 {
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compatible = "marvell,armada-3700-i2c", "simple-bus";
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reg = <0x0 0x11080 0x0 0x80>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins>;
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#address-cells = <2>;
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#size-cells = <2>;
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status = "okay";
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};
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uart1: serial@12200 {
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compatible = "marvell,armada-3700-uart-ext";
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reg = <0x0 0x12200 0x0 0x30>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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#address-cells = <2>;
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#size-cells = <2>;
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};
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vcc_sd_reg0: regulator@0 {
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compatible = "regulator-gpio";
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regulator-name = "vcc_sd0";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-type = "voltage";
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states = <1800000 0x1
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3300000 0x0>;
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gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
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};
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sfp_eth0: sfp-eth0 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
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};
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sfp_eth1: sfp-eth1 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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sfp,ethernet = <ð1>;
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los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
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};
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};
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&comphy {
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phy0 {
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phy-type = <COMPHY_TYPE_SGMII1>;
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phy-speed = <COMPHY_SPEED_1_25G>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_SGMII0>;
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phy-speed = <COMPHY_SPEED_1_25G>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_USB3_HOST1>;
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phy-speed = <COMPHY_SPEED_5G>;
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};
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};
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ð0 {
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pinctrl-0 = <&pcie_pins>;
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status = "okay";
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phy-mode = "2500base-x";
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managed = "in-band-status";
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phy = <ðphy0>;
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};
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ð1 {
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status = "okay";
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phy-mode = "2500base-x";
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managed = "in-band-status";
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phy = <ðphy1>;
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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};
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&spi0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi_quad_pins>;
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q1024a","n25q512a";
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reg = <0>;
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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m25p,fast-read;
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partition@0 {
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label = "uboot";
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reg = <0 0x400000>;
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};
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};
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};
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&sdhci1 {
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non-removable;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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bus-width = <4>;
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vqmmc-supply = <&vcc_sd_reg0>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdio_pins>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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mmccard: mmccard@0 {
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compatible = "mmc-card";
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reg = <0>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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&usb3 {
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status = "okay";
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};
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