mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
70a4da45e1
Original patch from Ralph Kondziella
plus clean up by Wolfgang Denk
plus changes by John Rigby
use ips clock not lpc
port forward to current u-boot release
Signed-off-by: Ralph Kondziella <rk@argos-messtechnik.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: John Rigby <jrigby@freescale.com>
663 lines
18 KiB
C
663 lines
18 KiB
C
/*
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* (C) Copyright 2007 DENX Software Engineering
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*
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* MPC512x Internal Memory Map
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Based on the MPC83xx header.
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*/
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#ifndef __IMMAP_512x__
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#define __IMMAP_512x__
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#include <asm/types.h>
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typedef struct law512x {
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u32 bar; /* Base Addr Register */
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u32 ar; /* Attributes Register */
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} law512x_t;
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/*
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* System configuration registers
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*/
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typedef struct sysconf512x {
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u32 immrbar; /* Internal memory map base address register */
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u8 res0[0x1c];
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u32 lpbaw; /* LP Boot Access Window */
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u32 lpcs0aw; /* LP CS0 Access Window */
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u32 lpcs1aw; /* LP CS1 Access Window */
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u32 lpcs2aw; /* LP CS2 Access Window */
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u32 lpcs3aw; /* LP CS3 Access Window */
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u32 lpcs4aw; /* LP CS4 Access Window */
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u32 lpcs5aw; /* LP CS5 Access Window */
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u32 lpcs6aw; /* LP CS6 Access Window */
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u32 lpcs7aw; /* LP CS7 Access Window */
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u8 res1[0x1c];
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law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
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u8 res2[0x28];
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law512x_t ddrlaw; /* DDR Local Access Window */
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u8 res3[0x18];
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u32 mbxbar; /* MBX Base Address */
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u32 srambar; /* SRAM Base Address */
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u32 nfcbar; /* NFC Base Address */
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u8 res4[0x34];
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u32 spridr; /* System Part and Revision ID Register */
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u32 spcr; /* System Priority Configuration Register */
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u8 res5[0xf8];
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} sysconf512x_t;
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/*
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* Watch Dog Timer (WDT) Registers
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*/
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typedef struct wdt512x {
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u8 res0[4];
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u32 swcrr; /* System watchdog control register */
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u32 swcnr; /* System watchdog count register */
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u8 res1[2];
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u16 swsrr; /* System watchdog service register */
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u8 res2[0xF0];
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} wdt512x_t;
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/*
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* RTC Module Registers
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*/
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typedef struct rtclk512x {
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u8 fixme[0x100];
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} rtclk512x_t;
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/*
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* General Purpose Timer
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*/
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typedef struct gpt512x {
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u8 fixme[0x100];
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} gpt512x_t;
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/*
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* Integrated Programmable Interrupt Controller
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*/
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typedef struct ipic512x {
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u8 fixme[0x100];
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} ipic512x_t;
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/*
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* System Arbiter Registers
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*/
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typedef struct arbiter512x {
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u32 acr; /* Arbiter Configuration Register */
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u32 atr; /* Arbiter Timers Register */
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u32 ater; /* Arbiter Transfer Error Register */
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u32 aer; /* Arbiter Event Register */
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u32 aidr; /* Arbiter Interrupt Definition Register */
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u32 amr; /* Arbiter Mask Register */
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u32 aeatr; /* Arbiter Event Attributes Register */
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u32 aeadr; /* Arbiter Event Address Register */
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u32 aerr; /* Arbiter Event Response Register */
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u8 res1[0xDC];
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} arbiter512x_t;
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/*
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* Reset Module
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*/
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typedef struct reset512x {
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u32 rcwl; /* Reset Configuration Word Low Register */
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u32 rcwh; /* Reset Configuration Word High Register */
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u8 res0[8];
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u32 rsr; /* Reset Status Register */
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u32 rmr; /* Reset Mode Register */
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u32 rpr; /* Reset protection Register */
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u32 rcr; /* Reset Control Register */
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u32 rcer; /* Reset Control Enable Register */
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u8 res1[0xDC];
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} reset512x_t;
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/*
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* Clock Module
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*/
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typedef struct clk512x {
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u32 spmr; /* System PLL Mode Register */
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u32 sccr[2]; /* System Clock Control Registers */
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u32 scfr[2]; /* System Clock Frequency Registers */
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u8 res0[4];
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u32 bcr; /* Bread Crumb Register */
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u32 pscccr[12]; /* PSC0-11 Clock Control Registers */
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u32 spccr; /* SPDIF Clock Control Registers */
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u32 cccr; /* CFM Clock Control Registers */
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u32 dccr; /* DIU Clock Control Registers */
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u8 res1[0xa8];
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} clk512x_t;
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/*
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* Power Management Control Module
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*/
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typedef struct pmc512x {
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u8 fixme[0x100];
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} pmc512x_t;
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/*
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* General purpose I/O module
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*/
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typedef struct gpio512x {
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u8 fixme[0x100];
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} gpio512x_t;
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/*
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* DDR Memory Controller Memory Map
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*/
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typedef struct ddr512x {
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u32 ddr_sys_config; /* System Configuration Register */
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u32 ddr_time_config0; /* Timing Configuration Register */
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u32 ddr_time_config1; /* Timing Configuration Register */
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u32 ddr_time_config2; /* Timing Configuration Register */
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u32 ddr_command; /* Command Register */
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u32 ddr_compact_command; /* Compact Command Register */
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u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */
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u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */
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u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */
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u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */
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u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */
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u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */
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u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */
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u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */
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u32 DQS_config_offset_count; /* DQS Config Offset Count */
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u32 DQS_config_offset_time; /* DQS Config Offset Time */
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u32 DQS_delay_status; /* DQS Delay Status */
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u32 res0[0xF];
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u32 prioman_config1; /* Priority Manager Configuration */
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u32 prioman_config2; /* Priority Manager Configuration */
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u32 hiprio_config; /* High Priority Configuration */
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u32 lut_table0_main_upper; /* LUT0 Main Upper */
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u32 lut_table1_main_upper; /* LUT1 Main Upper */
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u32 lut_table2_main_upper; /* LUT2 Main Upper */
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u32 lut_table3_main_upper; /* LUT3 Main Upper */
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u32 lut_table4_main_upper; /* LUT4 Main Upper */
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u32 lut_table0_main_lower; /* LUT0 Main Lower */
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u32 lut_table1_main_lower; /* LUT1 Main Lower */
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u32 lut_table2_main_lower; /* LUT2 Main Lower */
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u32 lut_table3_main_lower; /* LUT3 Main Lower */
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u32 lut_table4_main_lower; /* LUT4 Main Lower */
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u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */
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u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
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u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
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u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
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u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
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u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
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u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
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u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
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u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
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u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
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u32 performance_monitor_config;
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u32 event_time_counter;
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u32 event_time_preset;
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u32 performance_monitor1_address_low;
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u32 performance_monitor2_address_low;
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u32 performance_monitor1_address_hi;
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u32 performance_monitor2_address_hi;
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u32 res1[2];
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u32 performance_monitor1_read_counter;
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u32 performance_monitor2_read_counter;
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u32 performance_monitor1_write_counter;
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u32 performance_monitor2_write_counter;
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u32 granted_ack_counter0;
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u32 granted_ack_counter1;
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u32 granted_ack_counter2;
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u32 granted_ack_counter3;
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u32 granted_ack_counter4;
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u32 cumulative_wait_counter0;
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u32 cumulative_wait_counter1;
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u32 cumulative_wait_counter2;
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u32 cumulative_wait_counter3;
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u32 cumulative_wait_counter4;
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u32 summed_priority_counter0;
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u32 summed_priority_counter1;
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u32 summed_priority_counter2;
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u32 summed_priority_counter3;
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u32 summed_priority_counter4;
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u32 res2[0x3AD];
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} ddr512x_t;
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/*
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* DMA/Messaging Unit
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*/
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typedef struct dma512x {
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u8 fixme[0x1800];
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} dma512x_t;
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/*
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* PCI Software Configuration Registers
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*/
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typedef struct pciconf512x {
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u32 config_address;
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u32 config_data;
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u32 int_ack;
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u8 res[116];
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} pciconf512x_t;
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/*
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* PCI Outbound Translation Register
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*/
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typedef struct pci_outbound_window {
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u32 potar;
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u8 res0[4];
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u32 pobar;
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u8 res1[4];
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u32 pocmr;
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u8 res2[4];
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} pot512x_t;
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/*
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* Sequencer
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*/
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typedef struct ios512x {
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pot512x_t pot[6];
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u8 res0[0x60];
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u32 pmcr;
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u8 res1[4];
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u32 dtcr;
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u8 res2[4];
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} ios512x_t;
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/*
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* PCI Controller
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*/
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typedef struct pcictrl512x {
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u32 esr;
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u32 ecdr;
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u32 eer;
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u32 eatcr;
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u32 eacr;
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u32 eeacr;
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u32 edlcr;
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u32 edhcr;
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u32 gcr;
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u32 ecr;
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u32 gsr;
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u8 res0[12];
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u32 pitar2;
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u8 res1[4];
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u32 pibar2;
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u32 piebar2;
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u32 piwar2;
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u8 res2[4];
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u32 pitar1;
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u8 res3[4];
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u32 pibar1;
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u32 piebar1;
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u32 piwar1;
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u8 res4[4];
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u32 pitar0;
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u8 res5[4];
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u32 pibar0;
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u8 res6[4];
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u32 piwar0;
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u8 res7[132];
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} pcictrl512x_t;
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/*
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* MSCAN
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*/
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typedef struct mscan512x {
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u8 fixme[0x100];
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} mscan512x_t;
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/*
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* BDLC
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*/
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typedef struct bdlc512x {
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u8 fixme[0x100];
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} bdlc512x_t;
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/*
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* SDHC
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*/
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typedef struct sdhc512x {
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u8 fixme[0x100];
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} sdhc512x_t;
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/*
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* SPDIF
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*/
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typedef struct spdif512x {
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u8 fixme[0x100];
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} spdif512x_t;
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/*
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* I2C
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*/
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typedef struct i2c512x_dev {
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volatile u32 madr; /* I2Cn + 0x00 */
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volatile u32 mfdr; /* I2Cn + 0x04 */
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volatile u32 mcr; /* I2Cn + 0x08 */
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volatile u32 msr; /* I2Cn + 0x0C */
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volatile u32 mdr; /* I2Cn + 0x10 */
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u8 res0[0x0C];
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} i2c512x_dev_t;
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typedef struct i2c512x {
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i2c512x_dev_t dev[3];
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volatile u32 icr;
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volatile u32 mifr;
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u8 res0[0x98];
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} i2c512x_t;
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/*
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* AXE
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*/
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typedef struct axe512x {
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u8 fixme[0x100];
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} axe512x_t;
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/*
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* DIU
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*/
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typedef struct diu512x {
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u8 fixme[0x100];
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} diu512x_t;
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/*
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* CFM
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*/
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typedef struct cfm512x {
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u8 fixme[0x100];
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} cfm512x_t;
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/*
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* FEC
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*/
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typedef struct fec512x {
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u8 fixme[0x800];
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} fec512x_t;
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/*
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* ULPI
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*/
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typedef struct ulpi512x {
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u8 fixme[0x600];
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} ulpi512x_t;
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/*
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* UTMI
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*/
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typedef struct utmi512x {
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u8 fixme[0x3000];
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} utmi512x_t;
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/*
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* PCI DMA
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*/
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typedef struct pcidma512x {
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u8 fixme[0x300];
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} pcidma512x_t;
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/*
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* IO Control
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*/
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typedef struct ioctrl512x {
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u32 regs[0x400];
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} ioctrl512x_t;
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/*
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* IIM
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*/
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typedef struct iim512x {
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u32 stat; /* IIM status register */
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u32 statm; /* IIM status IRQ mask */
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u32 err; /* IIM errors register */
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u32 emask; /* IIM error IRQ mask */
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u32 fctl; /* IIM fuse control register */
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u32 ua; /* IIM upper address register */
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u32 la; /* IIM lower address register */
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u32 sdat; /* IIM explicit sense data */
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u8 res0[0x08];
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u32 prg_p; /* IIM program protection register */
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u8 res1[0x10];
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u32 divide; /* IIM divide factor register */
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u8 res2[0x7c0];
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u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */
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u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */
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u8 res3[0x380];
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u32 fbac1; /* IIM fuse bank 1 protection */
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u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */
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u8 res4[0x380];
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} iim512x_t;
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/*
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* LPC
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*/
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typedef struct lpc512x {
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u32 cs_cfg[8]; /* Chip Select N Configuration Registers
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No dedicated entry for CS Boot as == CS0 */
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u32 cs_cr; /* Chip Select Control Register */
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u32 cs_sr; /* Chip Select Status Register */
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u32 cs_bcr; /* Chip Select Burst Control Register */
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u32 cs_dccr; /* Chip Select Deadcycle Control Register */
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u32 cs_hccr; /* Chip Select Holdcycle Control Register */
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u8 res0[0xcc];
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u32 sclpc_psr; /* SCLPC Packet Size Register */
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u32 sclpc_sar; /* SCLPC Start Address Register */
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u32 sclpc_cr; /* SCLPC Control Register */
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u32 sclpc_er; /* SCLPC Enable Register */
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u32 sclpc_nar; /* SCLPC NextAddress Register */
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u32 sclpc_sr; /* SCLPC Status Register */
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u32 sclpc_bdr; /* SCLPC Bytes Done Register */
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u32 emb_scr; /* EMB Share Counter Register */
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u32 emb_pcr; /* EMB Pause Control Register */
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u8 res1[0x1c];
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u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */
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u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */
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u32 lpc_cr; /* LPC RX/TX FIFO Control Register */
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u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */
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u8 res2[0xb0];
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} lpc512x_t;
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/*
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* PATA
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*/
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typedef struct pata512x {
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/* LOCAL Registers */
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u32 pata_time1; /* Time register 1: PIO and tx timing parameter */
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u32 pata_time2; /* Time register 2: PIO timing parameter */
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u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */
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u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */
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u32 pata_time5; /* Time register 5: UDMA timing parameter */
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u32 pata_time6; /* Time register 6: UDMA timing parameter */
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u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */
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u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */
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u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/
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u32 pata_ata_control; /* ATA Interface control register */
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u32 pata_irq_pending; /* Interrupt pending register (READONLY) */
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u32 pata_irq_enable; /* Interrupt enable register */
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u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/
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u32 pata_fifo_alarm; /* fifo alarm threshold */
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u32 res1[0x1A];
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/* DRIVE Registers */
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u32 pata_drive_data; /* drive data register*/
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u32 pata_drive_features;/* drive features register */
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u32 pata_drive_sectcnt; /* drive sector count register */
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u32 pata_drive_sectnum; /* drive sector number register */
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u32 pata_drive_cyllow; /* drive cylinder low register */
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u32 pata_drive_cylhigh; /* drive cylinder high register */
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u32 pata_drive_dev_head;/* drive device head register */
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u32 pata_drive_command; /* write = drive command, read = drive status reg */
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u32 res2[0x06];
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u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
|
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u32 res3[0x09];
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} pata512x_t;
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|
|
|
/*
|
|
* PSC
|
|
*/
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|
typedef struct psc512x {
|
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volatile u8 mode; /* PSC + 0x00 */
|
|
volatile u8 res0[3];
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|
union { /* PSC + 0x04 */
|
|
volatile u16 status;
|
|
volatile u16 clock_select;
|
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} sr_csr;
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|
#define psc_status sr_csr.status
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|
#define psc_clock_select sr_csr.clock_select
|
|
volatile u16 res1;
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|
volatile u8 command; /* PSC + 0x08 */
|
|
volatile u8 res2[3];
|
|
union { /* PSC + 0x0c */
|
|
volatile u8 buffer_8;
|
|
volatile u16 buffer_16;
|
|
volatile u32 buffer_32;
|
|
} buffer;
|
|
#define psc_buffer_8 buffer.buffer_8
|
|
#define psc_buffer_16 buffer.buffer_16
|
|
#define psc_buffer_32 buffer.buffer_32
|
|
union { /* PSC + 0x10 */
|
|
volatile u8 ipcr;
|
|
volatile u8 acr;
|
|
} ipcr_acr;
|
|
#define psc_ipcr ipcr_acr.ipcr
|
|
#define psc_acr ipcr_acr.acr
|
|
volatile u8 res3[3];
|
|
union { /* PSC + 0x14 */
|
|
volatile u16 isr;
|
|
volatile u16 imr;
|
|
} isr_imr;
|
|
#define psc_isr isr_imr.isr
|
|
#define psc_imr isr_imr.imr
|
|
volatile u16 res4;
|
|
volatile u8 ctur; /* PSC + 0x18 */
|
|
volatile u8 res5[3];
|
|
volatile u8 ctlr; /* PSC + 0x1c */
|
|
volatile u8 res6[3];
|
|
volatile u32 ccr; /* PSC + 0x20 */
|
|
volatile u8 res7[12];
|
|
volatile u8 ivr; /* PSC + 0x30 */
|
|
volatile u8 res8[3];
|
|
volatile u8 ip; /* PSC + 0x34 */
|
|
volatile u8 res9[3];
|
|
volatile u8 op1; /* PSC + 0x38 */
|
|
volatile u8 res10[3];
|
|
volatile u8 op0; /* PSC + 0x3c */
|
|
volatile u8 res11[3];
|
|
volatile u32 sicr; /* PSC + 0x40 */
|
|
volatile u8 res12[60];
|
|
volatile u32 tfcmd; /* PSC + 0x80 */
|
|
volatile u32 tfalarm; /* PSC + 0x84 */
|
|
volatile u32 tfstat; /* PSC + 0x88 */
|
|
volatile u32 tfintstat; /* PSC + 0x8C */
|
|
volatile u32 tfintmask; /* PSC + 0x90 */
|
|
volatile u32 tfcount; /* PSC + 0x94 */
|
|
volatile u16 tfwptr; /* PSC + 0x98 */
|
|
volatile u16 tfrptr; /* PSC + 0x9A */
|
|
volatile u32 tfsize; /* PSC + 0x9C */
|
|
volatile u8 res13[28];
|
|
union { /* PSC + 0xBC */
|
|
volatile u8 buffer_8;
|
|
volatile u16 buffer_16;
|
|
volatile u32 buffer_32;
|
|
} tfdata_buffer;
|
|
#define tfdata_8 tfdata_buffer.buffer_8
|
|
#define tfdata_16 tfdata_buffer.buffer_16
|
|
#define tfdata_32 tfdata_buffer.buffer_32
|
|
|
|
volatile u32 rfcmd; /* PSC + 0xC0 */
|
|
volatile u32 rfalarm; /* PSC + 0xC4 */
|
|
volatile u32 rfstat; /* PSC + 0xC8 */
|
|
volatile u32 rfintstat; /* PSC + 0xCC */
|
|
volatile u32 rfintmask; /* PSC + 0xD0 */
|
|
volatile u32 rfcount; /* PSC + 0xD4 */
|
|
volatile u16 rfwptr; /* PSC + 0xD8 */
|
|
volatile u16 rfrptr; /* PSC + 0xDA */
|
|
volatile u32 rfsize; /* PSC + 0xDC */
|
|
volatile u8 res18[28];
|
|
union { /* PSC + 0xFC */
|
|
volatile u8 buffer_8;
|
|
volatile u16 buffer_16;
|
|
volatile u32 buffer_32;
|
|
} rfdata_buffer;
|
|
#define rfdata_8 rfdata_buffer.buffer_8
|
|
#define rfdata_16 rfdata_buffer.buffer_16
|
|
#define rfdata_32 rfdata_buffer.buffer_32
|
|
} psc512x_t;
|
|
|
|
/*
|
|
* FIFOC
|
|
*/
|
|
typedef struct fifoc512x {
|
|
u32 fifoc_cmd;
|
|
u32 fifoc_int;
|
|
u32 fifoc_dma;
|
|
u32 fifoc_axe;
|
|
u32 fifoc_debug;
|
|
u8 fixme[0xEC];
|
|
} fifoc512x_t;
|
|
|
|
/*
|
|
* SATA
|
|
*/
|
|
typedef struct sata512x {
|
|
u8 fixme[0x2000];
|
|
} sata512x_t;
|
|
|
|
typedef struct immap {
|
|
sysconf512x_t sysconf; /* System configuration */
|
|
u8 res0[0x700];
|
|
wdt512x_t wdt; /* Watch Dog Timer (WDT) */
|
|
rtclk512x_t rtc; /* Real Time Clock Module */
|
|
gpt512x_t gpt; /* General Purpose Timer */
|
|
ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */
|
|
arbiter512x_t arbiter; /* CSB Arbiter */
|
|
reset512x_t reset; /* Reset Module */
|
|
clk512x_t clk; /* Clock Module */
|
|
pmc512x_t pmc; /* Power Management Control Module */
|
|
gpio512x_t gpio; /* General purpose I/O module */
|
|
u8 res1[0x100];
|
|
mscan512x_t mscan; /* MSCAN */
|
|
bdlc512x_t bdlc; /* BDLC */
|
|
sdhc512x_t sdhc; /* SDHC */
|
|
spdif512x_t spdif; /* SPDIF */
|
|
i2c512x_t i2c; /* I2C Controllers */
|
|
u8 res2[0x800];
|
|
axe512x_t axe; /* AXE */
|
|
diu512x_t diu; /* Display Interface Unit */
|
|
cfm512x_t cfm; /* Clock Frequency Measurement */
|
|
u8 res3[0x500];
|
|
fec512x_t fec; /* Fast Ethernet Controller */
|
|
ulpi512x_t ulpi; /* USB ULPI */
|
|
u8 res4[0xa00];
|
|
utmi512x_t utmi; /* USB UTMI */
|
|
u8 res5[0x1000];
|
|
pcidma512x_t pci_dma; /* PCI DMA */
|
|
pciconf512x_t pci_conf; /* PCI Configuration */
|
|
u8 res6[0x80];
|
|
ios512x_t ios; /* PCI Sequencer */
|
|
pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */
|
|
u8 res7[0xa00];
|
|
ddr512x_t mddrc; /* Multi-port DDR Memory Controller */
|
|
ioctrl512x_t io_ctrl; /* IO Control */
|
|
iim512x_t iim; /* IC Identification module */
|
|
u8 res8[0x4000];
|
|
lpc512x_t lpc; /* LocalPlus Controller */
|
|
pata512x_t pata; /* Parallel ATA */
|
|
u8 res9[0xd00];
|
|
psc512x_t psc[12]; /* PSCs */
|
|
u8 res10[0x300];
|
|
fifoc512x_t fifoc; /* FIFO Controller */
|
|
u8 res11[0x2000];
|
|
dma512x_t dma; /* DMA */
|
|
u8 res12[0xa800];
|
|
sata512x_t sata; /* Serial ATA */
|
|
u8 res13[0xde000];
|
|
} immap_t;
|
|
#endif /* __IMMAP_512x__ */
|