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https://github.com/AsahiLinux/u-boot
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5a49f17481
Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
313 lines
6.9 KiB
C
313 lines
6.9 KiB
C
/* Only eth0 supported for now
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*
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* (C) Copyright 2003
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* Thomas.Lange@corelatus.se
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#if defined(CONFIG_SYS_DISCOVER_PHY)
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#error "PHY not supported yet"
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/* We just assume that we are running 100FD for now */
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/* We all use switches, right? ;-) */
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#endif
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/* I assume ethernet behaves like au1000 */
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#ifdef CONFIG_SOC_AU1000
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/* Base address differ between cpu:s */
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#define ETH0_BASE AU1000_ETH0_BASE
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#define MAC0_ENABLE AU1000_MAC0_ENABLE
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#else
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#ifdef CONFIG_SOC_AU1100
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#define ETH0_BASE AU1100_ETH0_BASE
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#define MAC0_ENABLE AU1100_MAC0_ENABLE
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#else
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#ifdef CONFIG_SOC_AU1500
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#define ETH0_BASE AU1500_ETH0_BASE
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#define MAC0_ENABLE AU1500_MAC0_ENABLE
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#else
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#ifdef CONFIG_SOC_AU1550
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#define ETH0_BASE AU1550_ETH0_BASE
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#define MAC0_ENABLE AU1550_MAC0_ENABLE
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#else
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#error "No valid cpu set"
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#endif
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#endif
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#endif
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#endif
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <command.h>
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#include <asm/io.h>
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#include <mach/au1x00.h>
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#if defined(CONFIG_CMD_MII)
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#include <miiphy.h>
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#endif
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/* Ethernet Transmit and Receive Buffers */
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#define DBUF_LENGTH 1520
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#define PKT_MAXBUF_SIZE 1518
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static char txbuf[DBUF_LENGTH];
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static int next_tx;
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static int next_rx;
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/* 4 rx and 4 tx fifos */
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#define NO_OF_FIFOS 4
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typedef struct{
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u32 status;
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u32 addr;
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u32 len; /* Only used for tx */
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u32 not_used;
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} mac_fifo_t;
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mac_fifo_t mac_fifo[NO_OF_FIFOS];
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#define MAX_WAIT 1000
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#if defined(CONFIG_CMD_MII)
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int au1x00_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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unsigned short value = 0;
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volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
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volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
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u32 mii_control;
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unsigned int timedout = 20;
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while (*mii_control_reg & MAC_MII_BUSY) {
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udelay(1000);
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if (--timedout == 0) {
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printf("au1x00_eth: miiphy_read busy timeout!!\n");
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return -1;
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}
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}
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mii_control = MAC_SET_MII_SELECT_REG(reg) |
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MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
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*mii_control_reg = mii_control;
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timedout = 20;
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while (*mii_control_reg & MAC_MII_BUSY) {
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udelay(1000);
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if (--timedout == 0) {
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printf("au1x00_eth: miiphy_read busy timeout!!\n");
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return -1;
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}
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}
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value = *mii_data_reg;
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return value;
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}
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int au1x00_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 value)
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{
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volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
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volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
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u32 mii_control;
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unsigned int timedout = 20;
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while (*mii_control_reg & MAC_MII_BUSY) {
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udelay(1000);
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if (--timedout == 0) {
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printf("au1x00_eth: miiphy_write busy timeout!!\n");
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return -1;
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}
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}
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mii_control = MAC_SET_MII_SELECT_REG(reg) |
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MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
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*mii_data_reg = value;
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*mii_control_reg = mii_control;
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return 0;
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}
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#endif
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static int au1x00_send(struct eth_device *dev, void *packet, int length)
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{
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volatile mac_fifo_t *fifo_tx =
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(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
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int i;
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int res;
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/* tx fifo should always be idle */
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fifo_tx[next_tx].len = length;
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fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
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au_sync();
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udelay(1);
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i=0;
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while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
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if(i>MAX_WAIT){
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printf("TX timeout\n");
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break;
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}
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udelay(1);
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i++;
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}
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/* Clear done bit */
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fifo_tx[next_tx].addr = 0;
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fifo_tx[next_tx].len = 0;
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au_sync();
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res = fifo_tx[next_tx].status;
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next_tx++;
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if(next_tx>=NO_OF_FIFOS){
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next_tx=0;
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}
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return(res);
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}
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static int au1x00_recv(struct eth_device* dev){
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volatile mac_fifo_t *fifo_rx =
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(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
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int length;
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u32 status;
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for(;;){
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if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
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/* Nothing has been received */
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return(-1);
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}
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status = fifo_rx[next_rx].status;
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length = status&0x3FFF;
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if(status&RX_ERROR){
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printf("Rx error 0x%x\n", status);
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} else {
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/* Pass the packet up to the protocol layers. */
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net_process_received_packet(net_rx_packets[next_rx],
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length - 4);
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}
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fifo_rx[next_rx].addr =
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(virt_to_phys(net_rx_packets[next_rx])) | RX_DMA_ENABLE;
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next_rx++;
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if(next_rx>=NO_OF_FIFOS){
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next_rx=0;
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}
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} /* for */
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return(0); /* Does anyone use this? */
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}
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static int au1x00_init(struct eth_device* dev, bd_t * bd){
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volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
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volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
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volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
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volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
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volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
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volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
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volatile mac_fifo_t *fifo_tx =
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(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
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volatile mac_fifo_t *fifo_rx =
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(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
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int i;
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next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
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next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
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/* We have to enable clocks before releasing reset */
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*macen = MAC_EN_CLOCK_ENABLE;
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udelay(10);
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/* Enable MAC0 */
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/* We have to release reset before accessing registers */
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*macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
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MAC_EN_RESET1|MAC_EN_RESET2;
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udelay(10);
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for(i=0;i<NO_OF_FIFOS;i++){
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fifo_tx[i].len = 0;
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fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
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fifo_rx[i].addr = (virt_to_phys(net_rx_packets[i])) |
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RX_DMA_ENABLE;
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}
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/* Put mac addr in little endian */
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#define ea eth_get_ethaddr()
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*mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
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*mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
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(ea[1] << 8) | (ea[0] ) ;
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#undef ea
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*mac_mcast_low = 0;
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*mac_mcast_high = 0;
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/* Make sure the MAC buffer is in the correct endian mode */
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#ifdef __LITTLE_ENDIAN
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*mac_ctrl = MAC_FULL_DUPLEX;
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udelay(1);
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*mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
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#else
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*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
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udelay(1);
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*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
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#endif
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return(1);
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}
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static void au1x00_halt(struct eth_device* dev){
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volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
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/* Put MAC0 in reset */
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*macen = 0;
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}
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int au1x00_enet_initialize(bd_t *bis){
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struct eth_device* dev;
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if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
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puts ("malloc failed\n");
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return -1;
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}
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memset(dev, 0, sizeof *dev);
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strcpy(dev->name, "Au1X00 ethernet");
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dev->iobase = 0;
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dev->priv = 0;
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dev->init = au1x00_init;
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dev->halt = au1x00_halt;
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dev->send = au1x00_send;
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dev->recv = au1x00_recv;
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eth_register(dev);
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#if defined(CONFIG_CMD_MII)
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int retval;
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struct mii_dev *mdiodev = mdio_alloc();
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
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mdiodev->read = au1x00_miiphy_read;
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mdiodev->write = au1x00_miiphy_write;
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retval = mdio_register(mdiodev);
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if (retval < 0)
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return retval;
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#endif
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return 1;
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}
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int cpu_eth_init(bd_t *bis)
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{
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au1x00_enet_initialize(bis);
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return 0;
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}
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