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https://github.com/AsahiLinux/u-boot
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78ba7b61da
All the code used to manage the mother boards will be common to soon to come CPU board. Move all that code into common.c Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
219 lines
4.3 KiB
C
219 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2010-2020 CS Group
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* Charles Frey <charles.frey@c-s.fr>
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* Florent Trinh Thai <florent.trinh-thai@c-s.fr>
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* Christophe Leroy <christophe.leroy@c-s.fr>
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*
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* Common specific routines for the CS Group boards
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*/
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#include <dm.h>
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#include <env.h>
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#include <fdt_support.h>
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#include <hang.h>
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#include <spi.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include "common.h"
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#define ADDR_FPGA_R_BASE ((unsigned char __iomem *)CONFIG_FPGA_BASE)
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#define FPGA_R_ACQ_AL_FAV 0x04
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#define TYPE_MCR 0x22
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#define TYPE_MIAE 0x23
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#define FAR_CASRSA 2
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#define FAR_VGOIP 4
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#define FAV_CLA 7
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#define FAV_SRSA 8
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#define SPI_EEPROM_READ 0x03
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static int fdt_set_node_and_value(void *blob, char *node, const char *prop,
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void *var, int size)
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{
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int ret, off;
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off = fdt_path_offset(blob, node);
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if (off < 0) {
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printf("Cannot find %s node err:%s\n", node, fdt_strerror(off));
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return off;
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}
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ret = fdt_setprop(blob, off, prop, var, size);
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if (ret < 0)
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printf("Cannot set %s/%s prop err: %s\n", node, prop, fdt_strerror(ret));
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return ret;
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}
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/* Checks front/rear id and remove unneeded nodes from the blob */
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static void ft_cleanup(void *blob, unsigned long id, const char *prop, const char *compatible)
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{
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int off;
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off = fdt_node_offset_by_compatible(blob, -1, compatible);
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while (off != -FDT_ERR_NOTFOUND) {
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const struct fdt_property *ids;
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int nb_ids, idx;
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int tmp = -1;
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ids = fdt_get_property(blob, off, prop, &nb_ids);
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for (idx = 0; idx < nb_ids; idx += 4) {
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if (*((uint32_t *)&ids->data[idx]) == id)
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break;
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}
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if (idx >= nb_ids)
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fdt_del_node(blob, off);
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else
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tmp = off;
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off = fdt_node_offset_by_compatible(blob, tmp, compatible);
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}
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fdt_set_node_and_value(blob, "/", prop, &id, sizeof(uint32_t));
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}
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int read_eeprom(u8 *din, int len)
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{
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struct udevice *eeprom;
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struct spi_slave *slave;
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uchar dout[3] = {SPI_EEPROM_READ, 0, 0};
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int ret;
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ret = uclass_get_device(UCLASS_SPI, 0, &eeprom);
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if (ret)
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return ret;
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ret = _spi_get_bus_and_cs(0, 0, 1000000, 0, "spi_generic_drv",
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"generic_0:0", &eeprom, &slave);
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if (ret)
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return ret;
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ret = spi_claim_bus(slave);
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ret = spi_xfer(slave, sizeof(dout) << 3, dout, NULL, SPI_XFER_BEGIN);
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if (ret)
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return ret;
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ret = spi_xfer(slave, len << 3, NULL, din, SPI_XFER_END);
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if (ret)
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return ret;
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spi_release_bus(slave);
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return 0;
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}
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int ft_board_setup_common(void *blob)
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{
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u8 far_id, fav_id;
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if (in_8(ADDR_FPGA_R_BASE) != TYPE_MIAE)
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return 0;
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far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
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ft_cleanup(blob, far_id, "far-id", "cs,mia-far");
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fav_id = in_8(ADDR_FPGA_R_BASE + 0x44) >> 5;
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if (far_id == FAR_CASRSA && fav_id == FAV_CLA)
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fav_id = FAV_SRSA;
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ft_cleanup(blob, fav_id, "fav-id", "cs,mia-fav");
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if (far_id == FAR_CASRSA)
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ft_board_setup_phy3();
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return 0;
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}
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int checkboard_common(void)
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{
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switch (in_8(ADDR_FPGA_R_BASE)) {
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int far_id;
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case TYPE_MCR:
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printf("MCR3000_2G (CS GROUP)\n");
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break;
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case TYPE_MIAE:
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far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
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if (far_id == FAR_VGOIP)
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printf("VGoIP (CS GROUP)\n");
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else
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printf("MIAE (CS GROUP)\n");
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break;
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default:
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printf("Unknown\n");
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for (;;)
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;
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break;
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}
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return 0;
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}
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void misc_init_r_common(void)
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{
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u8 tmp, far_id;
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int count = 3;
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switch (in_8(ADDR_FPGA_R_BASE)) {
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case TYPE_MCR:
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/* if at boot alarm button is pressed, delay boot */
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if ((in_8(ADDR_FPGA_R_BASE + 0x31) & FPGA_R_ACQ_AL_FAV) == 0)
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env_set("bootdelay", "60");
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env_set("config", CFG_BOARD_MCR3000_2G);
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env_set("hostname", CFG_BOARD_MCR3000_2G);
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break;
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case TYPE_MIAE:
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do {
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tmp = in_8(ADDR_FPGA_R_BASE + 0x41);
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count--;
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mdelay(10); /* 10msec wait */
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} while (count && tmp != in_8(ADDR_FPGA_R_BASE + 0x41));
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if (!count) {
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printf("Cannot read the reset factory switch position\n");
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hang();
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}
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if (tmp & 0x1)
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env_set_default("Factory settings switch ON", 0);
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env_set("config", CFG_BOARD_MIAE);
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far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
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if (far_id == FAR_VGOIP)
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env_set("hostname", CFG_BOARD_VGOIP);
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else
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env_set("hostname", CFG_BOARD_MIAE);
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break;
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default:
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env_set("config", CFG_BOARD_CMPCXXX);
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env_set("hostname", CFG_BOARD_CMPCXXX);
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break;
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}
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}
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void iop_setup_common(void)
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{
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u8 type = in_8(ADDR_FPGA_R_BASE);
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if (type == TYPE_MCR)
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iop_setup_mcr();
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else if (type == TYPE_MIAE)
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iop_setup_miae();
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}
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