mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-16 16:23:14 +00:00
5ad98c57b8
The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables the power for the Ethernet "MAC" (mostly PHY, really). In the DT this is described with the phy-supply property in the MAC DT node, pointing to a (GPIO controlled) regulator. Since we need Ethernet only in U-Boot proper, and use a DM driver there, we should use the DT instead of hardcoding this. Add code to the sun8i_emac and sunxi_emac drivers to check the DT for that regulator and enable it, at probe time. Then drop the current code from board.c, which was doing that job before. This allows us to remove the MACPWR Kconfig definition and the respective values from the defconfigs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com>
1068 lines
29 KiB
Text
1068 lines
29 KiB
Text
if ARCH_SUNXI
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config IDENT_STRING
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default " Allwinner Technology"
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config DRAM_SUN4I
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bool
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help
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Select this dram controller driver for Sun4/5/7i platforms,
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like A10/A13/A20.
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config DRAM_SUN6I
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bool
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help
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Select this dram controller driver for Sun6i platforms,
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like A31/A31s.
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config DRAM_SUN8I_A23
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bool
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help
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Select this dram controller driver for Sun8i platforms,
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for A23 SOC.
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config DRAM_SUN8I_A33
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bool
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help
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Select this dram controller driver for Sun8i platforms,
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for A33 SOC.
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config DRAM_SUN8I_A83T
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bool
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help
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Select this dram controller driver for Sun8i platforms,
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for A83T SOC.
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config DRAM_SUN9I
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bool
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help
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Select this dram controller driver for Sun9i platforms,
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like A80.
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config DRAM_SUN50I_H6
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bool
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help
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Select this dram controller driver for some sun50i platforms,
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like H6.
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config DRAM_SUN50I_H616
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bool
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help
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Select this dram controller driver for some sun50i platforms,
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like H616.
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if DRAM_SUN50I_H616
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config DRAM_SUN50I_H616_DX_ODT
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hex "H616 DRAM DX ODT parameter"
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help
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DX ODT value from vendor DRAM settings.
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config DRAM_SUN50I_H616_DX_DRI
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hex "H616 DRAM DX DRI parameter"
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help
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DX DRI value from vendor DRAM settings.
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config DRAM_SUN50I_H616_CA_DRI
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hex "H616 DRAM CA DRI parameter"
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help
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CA DRI value from vendor DRAM settings.
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config DRAM_SUN50I_H616_ODT_EN
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hex "H616 DRAM ODT EN parameter"
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default 0x1
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help
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ODT EN value from vendor DRAM settings.
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config DRAM_SUN50I_H616_TPR0
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hex "H616 DRAM TPR0 parameter"
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default 0x0
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help
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TPR0 value from vendor DRAM settings.
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config DRAM_SUN50I_H616_TPR2
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hex "H616 DRAM TPR2 parameter"
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default 0x0
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help
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TPR2 value from vendor DRAM settings.
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config DRAM_SUN50I_H616_TPR10
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hex "H616 DRAM TPR10 parameter"
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help
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TPR10 value from vendor DRAM settings. It tells which features
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should be configured, like write leveling, read calibration, etc.
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config DRAM_SUN50I_H616_TPR11
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hex "H616 DRAM TPR11 parameter"
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default 0x0
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help
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TPR11 value from vendor DRAM settings.
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config DRAM_SUN50I_H616_TPR12
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hex "H616 DRAM TPR12 parameter"
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default 0x0
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help
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TPR12 value from vendor DRAM settings.
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endif
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config SUN6I_PRCM
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bool
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help
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Support for the PRCM (Power/Reset/Clock Management) unit available
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in A31 SoC.
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config AXP_PMIC_BUS
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bool
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select DM_PMIC if DM_I2C
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select PMIC_AXP if DM_I2C
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help
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Select this PMIC bus access helpers for Sunxi platform PRCM or other
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AXP family PMIC devices.
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config SUNXI_SRAM_ADDRESS
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hex
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default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
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default 0x20000 if SUN50I_GEN_H6
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default 0x0
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---help---
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Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
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with the first SRAM region being located at address 0.
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Some newer SoCs map the boot ROM at address 0 instead and move the
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SRAM to a different address.
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config SUNXI_RVBAR_ADDRESS
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hex
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depends on ARM64
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default 0x09010040 if SUN50I_GEN_H6
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default 0x017000a0
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---help---
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The read-only RVBAR system register holds the address of the first
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instruction to execute after a reset. Allwinner cores provide a
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writable MMIO backing store for this register, to allow to set the
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entry point when switching to AArch64. This store is on different
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addresses, depending on the SoC.
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config SUNXI_RVBAR_ALTERNATIVE
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hex
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depends on ARM64
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default 0x08100040 if MACH_SUN50I_H616
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default SUNXI_RVBAR_ADDRESS
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---help---
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The H616 die exists in at least two variants, with one having the
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RVBAR registers at a different address. If the SoC variant ID
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(stored in SRAM_VER_REG[7:0]) is not 0, we need to use the
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other address.
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Set this alternative address to the same as the normal address
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for all other SoCs, so the content of the SRAM_VER_REG becomes
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irrelevant there, and we can use the same code.
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config SUNXI_A64_TIMER_ERRATUM
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bool
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# Note only one of these may be selected at a time! But hidden choices are
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# not supported by Kconfig
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config SUNXI_GEN_SUN4I
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bool
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---help---
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Select this for sunxi SoCs which have resets and clocks set up
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as the original A10 (mach-sun4i).
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config SUNXI_GEN_SUN6I
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bool
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---help---
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Select this for sunxi SoCs which have sun6i like periphery, like
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separate ahb reset control registers, custom pmic bus, new style
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watchdog, etc.
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config SUN50I_GEN_H6
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bool
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select FIT
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select SPL_LOAD_FIT
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select MMC_SUNXI_HAS_NEW_MODE
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select SUPPORT_SPL
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---help---
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Select this for sunxi SoCs which have H6 like peripherals, clocks
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and memory map.
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config SUNXI_DRAM_DW
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bool
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---help---
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Select this for sunxi SoCs which uses a DRAM controller like the
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DesignWare controller used in H3, mainly SoCs after H3, which do
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not have official open-source DRAM initialization code, but can
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use modified H3 DRAM initialization code.
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if SUNXI_DRAM_DW
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config SUNXI_DRAM_DW_16BIT
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bool
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---help---
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Select this for sunxi SoCs with DesignWare DRAM controller and
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have only 16-bit memory buswidth.
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config SUNXI_DRAM_DW_32BIT
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bool
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---help---
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Select this for sunxi SoCs with DesignWare DRAM controller with
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32-bit memory buswidth.
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endif
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config MACH_SUNXI_H3_H5
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bool
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select SUNXI_DE2
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select SUNXI_DRAM_DW
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select SUNXI_DRAM_DW_32BIT
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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# TODO: try out A80's 8GiB DRAM space
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config SUNXI_DRAM_MAX_SIZE
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hex
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default 0x100000000 if MACH_SUN50I_H616
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default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
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default 0x80000000
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choice
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prompt "Sunxi SoC Variant"
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optional
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config MACH_SUNIV
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bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
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select CPU_ARM926EJS
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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select SKIP_LOWLEVEL_INIT_ONLY
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select SPL_SKIP_LOWLEVEL_INIT_ONLY
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config MACH_SUN4I
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bool "sun4i (Allwinner A10)"
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select CPU_V7A
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select DRAM_SUN4I
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select SUNXI_GEN_SUN4I
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select SUPPORT_SPL
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imply SPL_SYS_I2C_LEGACY
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imply SYS_I2C_LEGACY
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config MACH_SUN5I
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bool "sun5i (Allwinner A13)"
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select CPU_V7A
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select DRAM_SUN4I
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select SUNXI_GEN_SUN4I
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select SUPPORT_SPL
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imply SPL_SYS_I2C_LEGACY
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imply SYS_I2C_LEGACY
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config MACH_SUN6I
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bool "sun6i (Allwinner A31)"
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SPL_ARMV7_SET_CORTEX_SMPEN
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select DRAM_SUN6I
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select SPL_I2C
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select SUN6I_PRCM
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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select SYS_I2C_SUN6I_P2WI
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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config MACH_SUN7I
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bool "sun7i (Allwinner A20)"
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SPL_ARMV7_SET_CORTEX_SMPEN
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select DRAM_SUN4I
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select SUNXI_GEN_SUN4I
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select SUPPORT_SPL
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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imply SPL_SYS_I2C_LEGACY
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imply SYS_I2C_LEGACY
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config MACH_SUN8I_A23
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bool "sun8i (Allwinner A23)"
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select DRAM_SUN8I_A23
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select SPL_I2C
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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select SYS_I2C_SUN8I_RSB
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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config MACH_SUN8I_A33
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bool "sun8i (Allwinner A33)"
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select DRAM_SUN8I_A33
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select SPL_I2C
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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select SYS_I2C_SUN8I_RSB
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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config MACH_SUN8I_A83T
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bool "sun8i (Allwinner A83T)"
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select CPU_V7A
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select DRAM_SUN8I_A83T
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select SPL_I2C
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select SUNXI_GEN_SUN6I
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select MMC_SUNXI_HAS_NEW_MODE
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select MMC_SUNXI_HAS_MODE_SWITCH
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select SUPPORT_SPL
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select SYS_I2C_SUN8I_RSB
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config MACH_SUN8I_H3
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bool "sun8i (Allwinner H3)"
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select MACH_SUNXI_H3_H5
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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config MACH_SUN8I_R40
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bool "sun8i (Allwinner R40)"
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SUNXI_GEN_SUN6I
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select MMC_SUNXI_HAS_NEW_MODE
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select SUPPORT_SPL
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select SUNXI_DRAM_DW
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select SUNXI_DRAM_DW_32BIT
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imply SPL_SYS_I2C_LEGACY
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config MACH_SUN8I_V3S
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bool "sun8i (Allwinner V3/V3s/S3/S3L)"
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select CPU_V7A
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SUNXI_GEN_SUN6I
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select SUNXI_DRAM_DW
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select SUNXI_DRAM_DW_16BIT
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select SUPPORT_SPL
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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config MACH_SUN9I
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bool "sun9i (Allwinner A80)"
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select CPU_V7A
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select SPL_ARMV7_SET_CORTEX_SMPEN
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select DRAM_SUN9I
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select SPL_I2C
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select SUN6I_PRCM
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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config MACH_SUN50I
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bool "sun50i (Allwinner A64)"
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select ARM64
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select SUN6I_PRCM
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select SUNXI_DE2
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select SUNXI_GEN_SUN6I
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select MMC_SUNXI_HAS_NEW_MODE
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select SUPPORT_SPL
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select SUNXI_DRAM_DW
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select SUNXI_DRAM_DW_32BIT
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select FIT
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select SPL_LOAD_FIT
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select SUNXI_A64_TIMER_ERRATUM
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config MACH_SUN50I_H5
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bool "sun50i (Allwinner H5)"
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select ARM64
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select MACH_SUNXI_H3_H5
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select MMC_SUNXI_HAS_NEW_MODE
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select FIT
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select SPL_LOAD_FIT
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config MACH_SUN50I_H6
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bool "sun50i (Allwinner H6)"
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select ARM64
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select DRAM_SUN50I_H6
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select SUN50I_GEN_H6
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config MACH_SUN50I_H616
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bool "sun50i (Allwinner H616)"
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select ARM64
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select DRAM_SUN50I_H616
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select SUN50I_GEN_H6
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endchoice
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# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
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config MACH_SUN8I
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bool
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select SPL_ARMV7_SET_CORTEX_SMPEN if !ARM64
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select SUN6I_PRCM
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default y if MACH_SUN8I_A23
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default y if MACH_SUN8I_A33
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default y if MACH_SUN8I_A83T
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default y if MACH_SUNXI_H3_H5
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default y if MACH_SUN8I_R40
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default y if MACH_SUN8I_V3S
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config RESERVE_ALLWINNER_BOOT0_HEADER
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bool "reserve space for Allwinner boot0 header"
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select ENABLE_ARM_SOC_BOOT0_HOOK
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---help---
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Prepend a 1536 byte (empty) header to the U-Boot image file, to be
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filled with magic values post build. The Allwinner provided boot0
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blob relies on this information to load and execute U-Boot.
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Only needed on 64-bit Allwinner boards so far when using boot0.
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config ARM_BOOT_HOOK_RMR
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bool
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depends on ARM64
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default y
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select ENABLE_ARM_SOC_BOOT0_HOOK
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---help---
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Insert some ARM32 code at the very beginning of the U-Boot binary
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which uses an RMR register write to bring the core into AArch64 mode.
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The very first instruction acts as a switch, since it's carefully
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chosen to be a NOP in one mode and a branch in the other, so the
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code would only be executed if not already in AArch64.
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This allows both the SPL and the U-Boot proper to be entered in
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either mode and switch to AArch64 if needed.
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if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616
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config SUNXI_DRAM_DDR3
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bool
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config SUNXI_DRAM_DDR2
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bool
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config SUNXI_DRAM_LPDDR3
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bool
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choice
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prompt "DRAM Type and Timing"
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default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
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default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
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config SUNXI_DRAM_DDR3_1333
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bool "DDR3 1333"
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select SUNXI_DRAM_DDR3
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---help---
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This option is the original only supported memory type, which suits
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many H3/H5/A64 boards available now.
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config SUNXI_DRAM_LPDDR3_STOCK
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bool "LPDDR3 with Allwinner stock configuration"
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select SUNXI_DRAM_LPDDR3
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---help---
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This option is the LPDDR3 timing used by the stock boot0 by
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Allwinner.
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config SUNXI_DRAM_H6_LPDDR3
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bool "LPDDR3 DRAM chips on the H6 DRAM controller"
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select SUNXI_DRAM_LPDDR3
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depends on DRAM_SUN50I_H6
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---help---
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This option is the LPDDR3 timing used by the stock boot0 by
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Allwinner.
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config SUNXI_DRAM_H6_DDR3_1333
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bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
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select SUNXI_DRAM_DDR3
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depends on DRAM_SUN50I_H6
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---help---
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This option is the DDR3 timing used by the boot0 on H6 TV boxes
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which use a DDR3-1333 timing.
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config SUNXI_DRAM_H616_LPDDR3
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bool "LPDDR3 DRAM chips on the H616 DRAM controller"
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select SUNXI_DRAM_LPDDR3
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depends on DRAM_SUN50I_H616
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help
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This option is the LPDDR3 timing used by the stock boot0 by
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Allwinner.
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config SUNXI_DRAM_H616_DDR3_1333
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bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
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select SUNXI_DRAM_DDR3
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depends on DRAM_SUN50I_H616
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help
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This option is the DDR3 timing used by the boot0 on H616 TV boxes
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which use a DDR3-1333 timing.
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config SUNXI_DRAM_DDR2_V3S
|
|
bool "DDR2 found in V3s chip"
|
|
select SUNXI_DRAM_DDR2
|
|
depends on MACH_SUN8I_V3S
|
|
---help---
|
|
This option is only for the DDR2 memory chip which is co-packaged in
|
|
Allwinner V3s SoC.
|
|
|
|
endchoice
|
|
endif
|
|
|
|
config DRAM_TYPE
|
|
int "sunxi dram type"
|
|
depends on MACH_SUN8I_A83T
|
|
default 3
|
|
---help---
|
|
Set the dram type, 3: DDR3, 7: LPDDR3
|
|
|
|
config DRAM_CLK
|
|
int "sunxi dram clock speed"
|
|
default 792 if MACH_SUN9I
|
|
default 648 if MACH_SUN8I_R40
|
|
default 312 if MACH_SUN6I || MACH_SUN8I
|
|
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
|
|
MACH_SUN8I_V3S
|
|
default 672 if MACH_SUN50I
|
|
default 744 if MACH_SUN50I_H6
|
|
default 720 if MACH_SUN50I_H616
|
|
---help---
|
|
Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
|
|
must be a multiple of 24. For the sun9i (A80), the tested values
|
|
(for DDR3-1600) are 312 to 792.
|
|
|
|
if MACH_SUN5I || MACH_SUN7I
|
|
config DRAM_MBUS_CLK
|
|
int "sunxi mbus clock speed"
|
|
default 300
|
|
---help---
|
|
Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
|
|
|
|
endif
|
|
|
|
config DRAM_ZQ
|
|
int "sunxi dram zq value"
|
|
depends on !MACH_SUN50I_H616
|
|
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
|
|
MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
|
|
default 127 if MACH_SUN7I
|
|
default 14779 if MACH_SUN8I_V3S
|
|
default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
|
|
default 4145117 if MACH_SUN9I
|
|
default 3881915 if MACH_SUN50I
|
|
---help---
|
|
Set the dram zq value.
|
|
|
|
config DRAM_ODT_EN
|
|
bool "sunxi dram odt enable"
|
|
depends on !MACH_SUN50I_H616
|
|
default y if MACH_SUN8I_A23
|
|
default y if MACH_SUNXI_H3_H5
|
|
default y if MACH_SUN8I_R40
|
|
default y if MACH_SUN50I
|
|
default y if MACH_SUN50I_H6
|
|
---help---
|
|
Select this to enable dram odt (on die termination).
|
|
|
|
if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
|
|
config DRAM_EMR1
|
|
int "sunxi dram emr1 value"
|
|
default 0 if MACH_SUN4I
|
|
default 4 if MACH_SUN5I || MACH_SUN7I
|
|
---help---
|
|
Set the dram controller emr1 value.
|
|
|
|
config DRAM_TPR3
|
|
hex "sunxi dram tpr3 value"
|
|
default 0x0
|
|
---help---
|
|
Set the dram controller tpr3 parameter. This parameter configures
|
|
the delay on the command lane and also phase shifts, which are
|
|
applied for sampling incoming read data. The default value 0
|
|
means that no phase/delay adjustments are necessary. Properly
|
|
configuring this parameter increases reliability at high DRAM
|
|
clock speeds.
|
|
|
|
config DRAM_DQS_GATING_DELAY
|
|
hex "sunxi dram dqs_gating_delay value"
|
|
default 0x0
|
|
---help---
|
|
Set the dram controller dqs_gating_delay parmeter. Each byte
|
|
encodes the DQS gating delay for each byte lane. The delay
|
|
granularity is 1/4 cycle. For example, the value 0x05060606
|
|
means that the delay is 5 quarter-cycles for one lane (1.25
|
|
cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
|
|
The default value 0 means autodetection. The results of hardware
|
|
autodetection are not very reliable and depend on the chip
|
|
temperature (sometimes producing different results on cold start
|
|
and warm reboot). But the accuracy of hardware autodetection
|
|
is usually good enough, unless running at really high DRAM
|
|
clocks speeds (up to 600MHz). If unsure, keep as 0.
|
|
|
|
choice
|
|
prompt "sunxi dram timings"
|
|
default DRAM_TIMINGS_VENDOR_MAGIC
|
|
---help---
|
|
Select the timings of the DDR3 chips.
|
|
|
|
config DRAM_TIMINGS_VENDOR_MAGIC
|
|
bool "Magic vendor timings from Android"
|
|
---help---
|
|
The same DRAM timings as in the Allwinner boot0 bootloader.
|
|
|
|
config DRAM_TIMINGS_DDR3_1066F_1333H
|
|
bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
|
|
---help---
|
|
Use the timings of the standard JEDEC DDR3-1066F speed bin for
|
|
DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
|
|
for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
|
|
used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
|
|
or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
|
|
that down binning to DDR3-1066F is supported (because DDR3-1066F
|
|
uses a bit faster timings than DDR3-1333H).
|
|
|
|
config DRAM_TIMINGS_DDR3_800E_1066G_1333J
|
|
bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
|
|
---help---
|
|
Use the timings of the slowest possible JEDEC speed bin for the
|
|
selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
|
|
DDR3-800E, DDR3-1066G or DDR3-1333J.
|
|
|
|
endchoice
|
|
|
|
endif
|
|
|
|
if MACH_SUN8I_A23
|
|
config DRAM_ODT_CORRECTION
|
|
int "sunxi dram odt correction value"
|
|
default 0
|
|
---help---
|
|
Set the dram odt correction value (range -255 - 255). In allwinner
|
|
fex files, this option is found in bits 8-15 of the u32 odt_en variable
|
|
in the [dram] section. When bit 31 of the odt_en variable is set
|
|
then the correction is negative. Usually the value for this is 0.
|
|
endif
|
|
|
|
config SYS_CLK_FREQ
|
|
default 408000000 if MACH_SUNIV
|
|
default 1008000000 if MACH_SUN4I
|
|
default 1008000000 if MACH_SUN5I
|
|
default 1008000000 if MACH_SUN6I
|
|
default 912000000 if MACH_SUN7I
|
|
default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
|
|
default 1008000000 if MACH_SUN8I
|
|
default 1008000000 if MACH_SUN9I
|
|
default 888000000 if MACH_SUN50I_H6
|
|
default 1008000000 if MACH_SUN50I_H616
|
|
|
|
config SYS_CONFIG_NAME
|
|
default "suniv" if MACH_SUNIV
|
|
default "sun4i" if MACH_SUN4I
|
|
default "sun5i" if MACH_SUN5I
|
|
default "sun6i" if MACH_SUN6I
|
|
default "sun7i" if MACH_SUN7I
|
|
default "sun8i" if MACH_SUN8I
|
|
default "sun9i" if MACH_SUN9I
|
|
default "sun50i" if MACH_SUN50I
|
|
default "sun50i" if MACH_SUN50I_H6
|
|
default "sun50i" if MACH_SUN50I_H616
|
|
|
|
config SYS_BOARD
|
|
default "sunxi"
|
|
|
|
config SYS_SOC
|
|
default "sunxi"
|
|
|
|
config SUNXI_MINIMUM_DRAM_MB
|
|
int "minimum DRAM size"
|
|
default 32 if MACH_SUNIV
|
|
default 64 if MACH_SUN8I_V3S
|
|
default 256
|
|
---help---
|
|
Minimum DRAM size expected on the board. Traditionally we assumed
|
|
256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM
|
|
we have smaller sizes, though, so that U-Boot's own load address and
|
|
the default payload addresses must be shifted down.
|
|
This is expected to be fixed by the SoC selection.
|
|
|
|
config UART0_PORT_F
|
|
bool "UART0 on MicroSD breakout board"
|
|
---help---
|
|
Repurpose the SD card slot for getting access to the UART0 serial
|
|
console. Primarily useful only for low level u-boot debugging on
|
|
tablets, where normal UART0 is difficult to access and requires
|
|
device disassembly and/or soldering. As the SD card can't be used
|
|
at the same time, the system can be only booted in the FEL mode.
|
|
Only enable this if you really know what you are doing.
|
|
|
|
config OLD_SUNXI_KERNEL_COMPAT
|
|
bool "Enable workarounds for booting old kernels"
|
|
---help---
|
|
Set this to enable various workarounds for old kernels, this results in
|
|
sub-optimal settings for newer kernels, only enable if needed.
|
|
|
|
config MMC1_PINS_PH
|
|
bool "Pins for mmc1 are on Port H"
|
|
depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
|
|
---help---
|
|
Select this option for boards where mmc1 uses the Port H pinmux.
|
|
|
|
config MMC_SUNXI_SLOT_EXTRA
|
|
int "mmc extra slot number"
|
|
default -1
|
|
---help---
|
|
sunxi builds always enable mmc0, some boards also have a second sdcard
|
|
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
|
|
support for this.
|
|
|
|
config USB0_VBUS_PIN
|
|
string "Vbus enable pin for usb0 (otg)"
|
|
default ""
|
|
---help---
|
|
Set the Vbus enable pin for usb0 (otg). This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config USB0_VBUS_DET
|
|
string "Vbus detect pin for usb0 (otg)"
|
|
default ""
|
|
---help---
|
|
Set the Vbus detect pin for usb0 (otg). This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config USB0_ID_DET
|
|
string "ID detect pin for usb0 (otg)"
|
|
default ""
|
|
---help---
|
|
Set the ID detect pin for usb0 (otg). This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config USB1_VBUS_PIN
|
|
string "Vbus enable pin for usb1 (ehci0)"
|
|
default "PH6" if MACH_SUN4I || MACH_SUN7I
|
|
default "PH27" if MACH_SUN6I
|
|
---help---
|
|
Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
|
|
a string in the format understood by sunxi_name_to_gpio, e.g.
|
|
PH1 for pin 1 of port H.
|
|
|
|
config USB2_VBUS_PIN
|
|
string "Vbus enable pin for usb2 (ehci1)"
|
|
default "PH3" if MACH_SUN4I || MACH_SUN7I
|
|
default "PH24" if MACH_SUN6I
|
|
---help---
|
|
See USB1_VBUS_PIN help text.
|
|
|
|
config USB3_VBUS_PIN
|
|
string "Vbus enable pin for usb3 (ehci2)"
|
|
default ""
|
|
---help---
|
|
See USB1_VBUS_PIN help text.
|
|
|
|
config I2C0_ENABLE
|
|
bool "Enable I2C/TWI controller 0"
|
|
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
|
|
default n if MACH_SUN6I || MACH_SUN8I
|
|
select CMD_I2C
|
|
---help---
|
|
This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
|
|
its clock and setting up the bus. This is especially useful on devices
|
|
with slaves connected to the bus or with pins exposed through e.g. an
|
|
expansion port/header.
|
|
|
|
config I2C1_ENABLE
|
|
bool "Enable I2C/TWI controller 1"
|
|
select CMD_I2C
|
|
---help---
|
|
See I2C0_ENABLE help text.
|
|
|
|
if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
|
|
config R_I2C_ENABLE
|
|
bool "Enable the PRCM I2C/TWI controller"
|
|
# This is used for the pmic on H3
|
|
default y if SY8106A_POWER
|
|
select CMD_I2C
|
|
---help---
|
|
Set this to y to enable the I2C controller which is part of the PRCM.
|
|
endif
|
|
|
|
config AXP_GPIO
|
|
bool "Enable support for gpio-s on axp PMICs"
|
|
depends on AXP_PMIC_BUS
|
|
---help---
|
|
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
|
|
|
|
config AXP_DISABLE_BOOT_ON_POWERON
|
|
bool "Disable device boot on power plug-in"
|
|
depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
|
|
default n
|
|
---help---
|
|
Say Y here to prevent the device from booting up because of a plug-in
|
|
event. When set, the device will boot into the SPL briefly to
|
|
determine why it was powered on, and if it was determined because of
|
|
a plug-in event instead of a button press event it will shut back off.
|
|
|
|
config VIDEO_SUNXI
|
|
bool "Enable graphical uboot console on HDMI, LCD or VGA"
|
|
depends on !MACH_SUN8I_A83T
|
|
depends on !MACH_SUNXI_H3_H5
|
|
depends on !MACH_SUN8I_R40
|
|
depends on !MACH_SUN8I_V3S
|
|
depends on !MACH_SUN9I
|
|
depends on !MACH_SUN50I
|
|
depends on !SUN50I_GEN_H6
|
|
select VIDEO
|
|
select DISPLAY
|
|
imply VIDEO_DT_SIMPLEFB
|
|
default y
|
|
---help---
|
|
Say Y here to add support for using a graphical console on the HDMI,
|
|
LCD or VGA output found on older sunxi devices. This will also provide
|
|
a simple_framebuffer device for Linux.
|
|
|
|
config VIDEO_HDMI
|
|
bool "HDMI output support"
|
|
depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
|
|
default y
|
|
---help---
|
|
Say Y here to add support for outputting video over HDMI.
|
|
|
|
config VIDEO_VGA
|
|
bool "VGA output support"
|
|
depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
|
|
---help---
|
|
Say Y here to add support for outputting video over VGA.
|
|
|
|
config VIDEO_VGA_VIA_LCD
|
|
bool "VGA via LCD controller support"
|
|
depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
|
|
---help---
|
|
Say Y here to add support for external DACs connected to the parallel
|
|
LCD interface driving a VGA connector, such as found on the
|
|
Olimex A13 boards.
|
|
|
|
config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
|
|
bool "Force sync active high for VGA via LCD controller support"
|
|
depends on VIDEO_VGA_VIA_LCD
|
|
---help---
|
|
Say Y here if you've a board which uses opendrain drivers for the vga
|
|
hsync and vsync signals. Opendrain drivers cannot generate steep enough
|
|
positive edges for a stable video output, so on boards with opendrain
|
|
drivers the sync signals must always be active high.
|
|
|
|
config VIDEO_VGA_EXTERNAL_DAC_EN
|
|
string "LCD panel power enable pin"
|
|
depends on VIDEO_VGA_VIA_LCD
|
|
default ""
|
|
---help---
|
|
Set the enable pin for the external VGA DAC. This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config VIDEO_COMPOSITE
|
|
bool "Composite video output support"
|
|
depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
|
|
---help---
|
|
Say Y here to add support for outputting composite video.
|
|
|
|
config VIDEO_LCD_MODE
|
|
string "LCD panel timing details"
|
|
depends on VIDEO_SUNXI
|
|
default ""
|
|
---help---
|
|
LCD panel timing details string, leave empty if there is no LCD panel.
|
|
This is in drivers/video/videomodes.c: video_get_params() format, e.g.
|
|
x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
|
|
Also see: http://linux-sunxi.org/LCD
|
|
|
|
config VIDEO_LCD_DCLK_PHASE
|
|
int "LCD panel display clock phase"
|
|
depends on VIDEO_SUNXI || VIDEO
|
|
default 1
|
|
range 0 3
|
|
---help---
|
|
Select LCD panel display clock phase shift
|
|
|
|
config VIDEO_LCD_POWER
|
|
string "LCD panel power enable pin"
|
|
depends on VIDEO_SUNXI
|
|
default ""
|
|
---help---
|
|
Set the power enable pin for the LCD panel. This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config VIDEO_LCD_RESET
|
|
string "LCD panel reset pin"
|
|
depends on VIDEO_SUNXI
|
|
default ""
|
|
---help---
|
|
Set the reset pin for the LCD panel. This takes a string in the format
|
|
understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config VIDEO_LCD_BL_EN
|
|
string "LCD panel backlight enable pin"
|
|
depends on VIDEO_SUNXI
|
|
default ""
|
|
---help---
|
|
Set the backlight enable pin for the LCD panel. This takes a string in the
|
|
the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
|
|
port H.
|
|
|
|
config VIDEO_LCD_BL_PWM
|
|
string "LCD panel backlight pwm pin"
|
|
depends on VIDEO_SUNXI
|
|
default ""
|
|
---help---
|
|
Set the backlight pwm pin for the LCD panel. This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config VIDEO_LCD_BL_PWM_ACTIVE_LOW
|
|
bool "LCD panel backlight pwm is inverted"
|
|
depends on VIDEO_SUNXI
|
|
default y
|
|
---help---
|
|
Set this if the backlight pwm output is active low.
|
|
|
|
config VIDEO_LCD_PANEL_I2C
|
|
bool "LCD panel needs to be configured via i2c"
|
|
depends on VIDEO_SUNXI
|
|
select DM_I2C_GPIO
|
|
---help---
|
|
Say y here if the LCD panel needs to be configured via i2c. This
|
|
will add a bitbang i2c controller using gpios to talk to the LCD.
|
|
|
|
config VIDEO_LCD_PANEL_I2C_NAME
|
|
string "LCD panel i2c interface node name"
|
|
depends on VIDEO_LCD_PANEL_I2C
|
|
default "i2c"
|
|
---help---
|
|
Set the device tree node name for the LCD i2c interface.
|
|
|
|
# Note only one of these may be selected at a time! But hidden choices are
|
|
# not supported by Kconfig
|
|
config VIDEO_LCD_IF_PARALLEL
|
|
bool
|
|
|
|
config VIDEO_LCD_IF_LVDS
|
|
bool
|
|
|
|
config SUNXI_DE2
|
|
bool
|
|
|
|
config VIDEO_DE2
|
|
bool "Display Engine 2 video driver"
|
|
depends on SUNXI_DE2
|
|
select VIDEO
|
|
select DISPLAY
|
|
select VIDEO_DW_HDMI
|
|
imply VIDEO_DT_SIMPLEFB
|
|
default y
|
|
---help---
|
|
Say y here if you want to build DE2 video driver which is present on
|
|
newer SoCs. Currently only HDMI output is supported.
|
|
|
|
|
|
choice
|
|
prompt "LCD panel support"
|
|
depends on VIDEO_SUNXI
|
|
---help---
|
|
Select which type of LCD panel to support.
|
|
|
|
config VIDEO_LCD_PANEL_PARALLEL
|
|
bool "Generic parallel interface LCD panel"
|
|
select VIDEO_LCD_IF_PARALLEL
|
|
|
|
config VIDEO_LCD_PANEL_LVDS
|
|
bool "Generic lvds interface LCD panel"
|
|
select VIDEO_LCD_IF_LVDS
|
|
|
|
config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
|
|
bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
|
|
select VIDEO_LCD_SSD2828
|
|
select VIDEO_LCD_IF_PARALLEL
|
|
---help---
|
|
7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
|
|
|
|
config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
|
|
bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
|
|
select VIDEO_LCD_ANX9804
|
|
select VIDEO_LCD_IF_PARALLEL
|
|
select VIDEO_LCD_PANEL_I2C
|
|
---help---
|
|
Select this for eDP LCD panels with 4 lanes running at 1.62G,
|
|
connected via an ANX9804 bridge chip.
|
|
|
|
config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
|
|
bool "Hitachi tx18d42vm LCD panel"
|
|
select VIDEO_LCD_HITACHI_TX18D42VM
|
|
select VIDEO_LCD_IF_LVDS
|
|
---help---
|
|
7.85" 1024x768 Hitachi tx18d42vm LCD panel support
|
|
|
|
config VIDEO_LCD_TL059WV5C0
|
|
bool "tl059wv5c0 LCD panel"
|
|
select VIDEO_LCD_PANEL_I2C
|
|
select VIDEO_LCD_IF_PARALLEL
|
|
---help---
|
|
6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
|
|
Aigo M60/M608/M606 tablets.
|
|
|
|
endchoice
|
|
|
|
config GMAC_TX_DELAY
|
|
int "GMAC Transmit Clock Delay Chain"
|
|
default 0
|
|
---help---
|
|
Set the GMAC Transmit Clock Delay Chain value.
|
|
|
|
config SPL_STACK_R_ADDR
|
|
default 0x81e00000 if MACH_SUNIV
|
|
default 0x4fe00000 if MACH_SUN4I
|
|
default 0x4fe00000 if MACH_SUN5I
|
|
default 0x4fe00000 if MACH_SUN6I
|
|
default 0x4fe00000 if MACH_SUN7I
|
|
default 0x4fe00000 if MACH_SUN8I
|
|
default 0x2fe00000 if MACH_SUN9I
|
|
default 0x4fe00000 if MACH_SUN50I
|
|
default 0x4fe00000 if SUN50I_GEN_H6
|
|
|
|
config SPL_SPI_SUNXI
|
|
bool "Support for SPI Flash on Allwinner SoCs in SPL"
|
|
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV
|
|
help
|
|
Enable support for SPI Flash. This option allows SPL to read from
|
|
sunxi SPI Flash. It uses the same method as the boot ROM, so does
|
|
not need any extra configuration.
|
|
|
|
config PINE64_DT_SELECTION
|
|
bool "Enable Pine64 device tree selection code"
|
|
depends on MACH_SUN50I
|
|
help
|
|
The original Pine A64 and Pine A64+ are similar but different
|
|
boards and can be differed by the DRAM size. Pine A64 has
|
|
512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
|
|
option, the device tree selection code specific to Pine64 which
|
|
utilizes the DRAM size will be enabled.
|
|
|
|
config PINEPHONE_DT_SELECTION
|
|
bool "Enable PinePhone device tree selection code"
|
|
depends on MACH_SUN50I
|
|
help
|
|
Enable this option to automatically select the device tree for the
|
|
correct PinePhone hardware revision during boot.
|
|
|
|
config BLUETOOTH_DT_DEVICE_FIXUP
|
|
string "Fixup the Bluetooth controller address"
|
|
default ""
|
|
help
|
|
This option specifies the DT compatible name of the Bluetooth
|
|
controller for which to set the "local-bd-address" property.
|
|
Set this option if your device ships with the Bluetooth controller
|
|
default address.
|
|
The used address is "bdaddr" if set, and "ethaddr" with the LSB
|
|
flipped elsewise.
|
|
|
|
source "board/sunxi/Kconfig"
|
|
|
|
endif
|
|
|
|
config CHIP_DIP_SCAN
|
|
bool "Enable DIPs detection for CHIP board"
|
|
select SUPPORT_EXTENSION_SCAN
|
|
select W1
|
|
select W1_GPIO
|
|
select W1_EEPROM
|
|
select W1_EEPROM_DS24XXX
|
|
select CMD_EXTENSION
|