mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
aaf224ab4e
- Add support for the SSV ADNP/ESC1 (Nios Softcore) * Patch by George G. Davis, 9 Mar 2004: fix recent build failure for SA1100 target * Patch by Travis Sawyer, 09 Mar 2004: Support native interrupt mode for the IBM440GX. Previously it was running in 440GP compatibility mode.
469 lines
19 KiB
Text
469 lines
19 KiB
Text
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TODO: specify IDE i/f
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===============================================================================
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C P U , M E M O R Y , I N / O U T C O M P O N E N T S
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===============================================================================
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see also [1]-[5]
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CPU: "DNP_ESC1"
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32 bit NIOS for 50 MHz
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512 Byte for register file (30 levels)
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with out instruction cache
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with out data cache
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2 KByte On Chip ROM with GERMS boot monitor
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with out On Chip RAM
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MSTEP multiplier
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no Debug Core
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no On Chip Instrumentation (OCI)
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U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
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CFG_NIOS_CPU_ICACHE = (not present)
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CFG_NIOS_CPU_DCACHE = (not present)
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CFG_NIOS_CPU_REG_NUMS = 512
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CFG_NIOS_CPU_MUL = 0
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CFG_NIOS_CPU_MSTEP = 1
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CFG_NIOS_CPU_DBG_CORE = 0
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IRQ: Nr. | used by
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------+--------------------------------------------------------
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16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16
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17 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 17
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18 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 18
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20 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ =
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| PIO6 | CFG_NIOS_CPU_PIO6_IRQ = 20
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25 | SPI0 | CFG_NIOS_CPU_SPI0_IRQ = 25
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31 | PIO7 | CFG_NIOS_CPU_PIO7_IRQ = 31
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32 | PIO8 | CFG_NIOS_CPU_PIO8_IRQ = 32
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33 | PIO9 | CFG_NIOS_CPU_PIO9_IRQ = 33
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34 | PIO10 | CFG_NIOS_CPU_PIO10_IRQ = 34
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35 | PIO11 | CFG_NIOS_CPU_PIO11_IRQ = 35
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36 | PIO12 | CFG_NIOS_CPU_PIO12_IRQ =
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| IDE0 | CFG_NIOS_CPU_IDE0_IRQ = 36
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37 | PIO13 | CFG_NIOS_CPU_PIO13_IRQ =
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| IDE1 | CFG_NIOS_CPU_IDE1_IRQ = 37
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MEMORY: 8 MByte Flash
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16 MByte SDRAM
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Timer: TIMER0: high priority programmable timer (IRQ16)
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U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0
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CFG_NIOS_CPU_USER_TIMER = (not present)
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PIO: Nr. | description
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------+--------------------------------------------------------
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PIO0 | PORTA: 8 in/outputs for general purpose usage
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PIO1 | PORTB: 8 in/outputs for general purpose usage
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PIO2 | PORTC: 4 in/outputs for general purpose usage
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PIO3 | RCM: 1 input for RCM_EN# jumper (Req.Conf.Mon.)
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PIO4 | WDTENA: 1 output to enable the on-board watchdog
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PIO5 | WDTTRIG: 1 output to trigger the on-board watchdog
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PIO6 | LAN0INT: 1 input for LAN91C111 irq input (IRQ20)
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PIO7 | INT1: 1 input for general purpose irq (IRQ31)
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PIO8 | INT2: 1 input for general purpose irq (IRQ32)
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PIO9 | INT3: 1 input for general purpose irq (IRQ33)
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PIO10| INT4: 1 input for general purpose irq (IRQ34)
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PIO11| INT5: 1 input for general purpose irq (IRQ35)
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PIO12| INT6: 1 input for general purpose irq (IRQ36)
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| IDE0INT: (same) for IDE0 irq input
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PIO13| INT7: 1 input for general purpose irq (IRQ37)
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| IDE1INT: (same) for IDE1 irq input
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U-Boot CFG: CFG_NIOS_CPU_PORTA_PIO = 0
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CFG_NIOS_CPU_PORTB_PIO = 1
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CFG_NIOS_CPU_PORTC_PIO = 2
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CFG_NIOS_CPU_RCM_PIO = 3
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CFG_NIOS_CPU_WDTENA_PIO = 4
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CFG_NIOS_CPU_WDTTRIG_PIO = 5
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CFG_NIOS_CPU_LED_PIO = (not present)
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UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, RTS/CTS (IRQ17)
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UART1: fixed baudrate of 115200, fixed protocol 8N1,
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without handshake RTS/CTS (IRQ18)
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SPI: SPI0: master capable, 1 slave selectable, 250kHz target clock,
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2 usec targets delay between slave select and clock,
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data is transferred MSB-first / LSB-last (IRQ25)
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LAN: SMsC LAN91C111 with:
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- without offset
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- data bus width 16 bit (on-board hard wired at 32 bit bus)
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- !!! 32 bit bus access --> each address * 2 !!!
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IDE: (TODO)
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===============================================================================
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M E M O R Y M A P
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===============================================================================
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- - - - - - - - - - - external extension - - - - - - - - - - - - - - - - - - -
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0x44000000 ---32-----------16|15------------0-
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: (real size : : |
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EXT3 (CS4) : and content : : > CFG_NIOS_CPU_CS3_SIZE
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: unknown) : : | = 0x01000000
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| | | /
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0x43000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS3_BASE
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: (real size : : |
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EXT2 (CS3) : and content : : > CFG_NIOS_CPU_CS2_SIZE
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: unknown) : : | = 0x01000000
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0x42000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS2_BASE
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: (real size : : |
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EXT1 (CS2) : and content : : > CFG_NIOS_CPU_CS1_SIZE
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: unknown) : : | = 0x01000000
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0x41000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS1_BASE
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: (real size : : |
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EXT0 (CS1) : and content : : > CFG_NIOS_CPU_CS0_SIZE
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: unknown) : : | = 0x01000000
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0x40000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS0_BASE
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: gap :
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: :
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- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - -
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: :
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: gap :
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0x03000000 ---32-----------16|15------------0- CFG_NIOS_CPU_STACK
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| . | \
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| . | | (U-Boot run-time system)
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| . | |
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| . | > CFG_MONITOR_LEN
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| . | | = 0x00040000
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| . | |
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| . | /
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0x02fc0000 --+32-----------16|15------------0+ TEXT_BASE
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| . | \
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| . | > CFG_MALLOC_LEN (heap)
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| . | /
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--+32-----------16|15------------0+
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| . | \
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| . | > CFG_GBL_DATA_SIZE (global)
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| . | /
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--+32-----------16|15------------0+ CFG_INIT_SP (u-boot stack)
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| . | \ \
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| . | | |
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| . | | > stack area
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| . | | |
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| . | | V
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| . | |
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| . | |
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SDRAM | . | > CFG_NIOS_CPU_SDRAM_SIZE
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| . | | = 0x01000000
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| . | |
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0x02000100 |- - - - - - - - - - - - - - - -+-|-
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| . | | |
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| . | | > CFG_NIOS_CPU_VEC_SIZE
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| . | | | = 0x00000100
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| | / /
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0x02000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE
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0x02000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE
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: gap : > (space for 2nd Flash)
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0x01800000 ---32-----------16|15------------0-
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| sector 127 | \
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+ 0x7f0000 |- - - - - - - - - - - - - - - -| |
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| : | |
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Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE
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| sector 1 : | | = 0x00800000
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+ 0x010000 |- - - - - - - - - - - - - - - -| |
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| sector 0 (size = 0x10000) | /
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0x01000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE
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: gap :
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: :
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- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
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: :
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: gap :
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0x00010020 ---32-----------16|15------------0-
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| register bank | |
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| size = (real_size << 1) | |
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| real_size = 0x10 | |
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| +--------.---.---.--- | |
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| | bank 0 \ 1 \ 2 \ 3 \ | |
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| |---------------------------+ | |
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LAN91C111 | | BANK | RESERVED | | > na_enet_size
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| |- - - - - - -|- - - - - - -| | | = 0x00000020
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| | RPCR | MIR | | |
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| |- - - - - - -|- - - - - - -| | |
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| | COUNTER | RCR | | |
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| |- - - - - - -|- - - - - - -| | |
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| | EPH STATUS | TCR | | |
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| +---------------------------+ | /
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0x00010000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE
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: gap :
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: :
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- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
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: :
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: gap :
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0x00001040 ---32-----------16|15------------0-
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: : : |
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IDE1 i/f : : : > 0x00000020
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[5] : : : |
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0x00001020 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE1
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: : : |
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IDE0 i/f : : : > 0x00000020
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[5] : : : |
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0x00001000 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0
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: gap :
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0x00000980 ---32-----------16|15------------0-
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| edgecapture (1 bit) (rw) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO13 | interruptmask (1 bit) (rw) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (1 bit) (ro) | /
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0x00000970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO13
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| edgecapture (1 bit) (rw) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO12 | interruptmask (1 bit) (rw) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (1 bit) (ro) | /
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0x00000960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO12
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| edgecapture (1 bit) (rw) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO11 | interruptmask (1 bit) (rw) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (1 bit) (ro) | /
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0x00000950 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO11
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| edgecapture (1 bit) (rw) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO10 | interruptmask (1 bit) (rw) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (1 bit) (ro) | /
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0x00000940 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO10
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| edgecapture (1 bit) (rw) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO9 | interruptmask (1 bit) (rw) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (1 bit) (ro) | /
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0x00000930 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO9
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| edgecapture (1 bit) (rw) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO8 | interruptmask (1 bit) (rw) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (1 bit) (ro) | /
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0x00000920 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO8
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| edgecapture (1 bit) (rw) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO7 | interruptmask (1 bit) (rw) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (1 bit) (ro) | /
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0x00000910 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7
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| edgecapture (1 bit) (rw) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO6 | interruptmask (1 bit) (rw) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (1 bit) (ro) | /
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0x00000900 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6
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: gap :
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0x000008e0 ---32-----------16|15------------0-
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| (unused) | \
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+ 0x1c |- - - - - - - - - - - - - - - -| |
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| endofpacket (16 bit) (rw) | |
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+ 0x18 |- - - - - - - - - - - - - - - -| |
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| slaveselect (1 bit) (rw) | |
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+ 0x14 |- - - - - - - - - - - - - - - -| |
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SPI0 | (reserved) | |
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[4] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
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| control (11 bit) (rw) | |
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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| status (9 bit) (rw) | |
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+ 0x08 |- - - - - - - - - - - - - - - -| |
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| txdata (16 bit) (wo) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| rxdata (16 bit) (ro) | /
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0x000008c0 ---32-----------16|15------------0- CFG_NIOS_CPU_SPI0
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| (unused) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO5 | (unused) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (1 bit) (wo) | /
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0x000008b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5
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| (unused) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO4 | (unused) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (1 bit) (wo) | /
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0x000008a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4
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| (unused) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO3 | (unused) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (1 bit) (ro) | /
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0x00000890 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
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| (unused) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO2 | (unused) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| direction (4 bit) (rw) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (4 bit) (rw) | /
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0x00000880 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
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| (unused) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO1 | (unused) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| direction (8 bit) (rw) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (8 bit) (rw) | /
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0x00000870 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
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| (unused) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO0 | (unused) | |
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[3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| direction (8 bit) (rw) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (8 bit) (rw) | /
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0x00000860 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
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| (unused) | \
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+ 0x1c |- - - - - - - - - - - - - - - -| |
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| (unused) | |
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+ 0x18 |- - - - - - - - - - - - - - - -| |
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| snaph (16 bit) (rw) | |
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+ 0x14 |- - - - - - - - - - - - - - - -| |
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TIMER0 | snapl (16 bit) (rw) | |
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[2] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
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| periodh (16 bit) (rw) | |
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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| periodl (16 bit) (rw) | |
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+ 0x08 |- - - - - - - - - - - - - - - -| |
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| control (4 bit) (rw) | |
|
|
+ 0x04 |- - - - - - - - - - - - - - - -| |
|
|
| status (2 bit) (rw) | /
|
|
0x00000840 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
|
|
| (unused) | \
|
|
+ 0x1c |- - - - - - - - - - - - - - - -| |
|
|
| (unused) | |
|
|
+ 0x18 |- - - - - - - - - - - - - - - -| |
|
|
| (unused) | |
|
|
+ 0x14 |- - - - - - - - - - - - - - - -| |
|
|
UART1 | (unused) | > 0x00000020
|
|
[1] + 0x10 |- - - - - - - - - - - - - - - -| |
|
|
| control (10 bit) (rw) | |
|
|
+ 0x0c |- - - - - - - - - - - - - - - -| |
|
|
| status (10 bit) (rw) | |
|
|
+ 0x08 |- - - - - - - - - - - - - - - -| |
|
|
| txdata (8 bit) (wo) | |
|
|
+ 0x04 |- - - - - - - - - - - - - - - -| |
|
|
| rxdata (8 bit) (ro) | /
|
|
0x00000820 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1
|
|
| (unused) | \
|
|
+ 0x1c |- - - - - - - - - - - - - - - -| |
|
|
| (unused) | |
|
|
+ 0x18 |- - - - - - - - - - - - - - - -| |
|
|
| (unused) | |
|
|
+ 0x14 |- - - - - - - - - - - - - - - -| |
|
|
UART0 | (unused) | > 0x00000020
|
|
[1] + 0x10 |- - - - - - - - - - - - - - - -| |
|
|
| control (10 bit) (rw) | |
|
|
+ 0x0c |- - - - - - - - - - - - - - - -| |
|
|
| status (10 bit) (rw) | |
|
|
+ 0x08 |- - - - - - - - - - - - - - - -| |
|
|
| txdata (8 bit) (wo) | |
|
|
+ 0x04 |- - - - - - - - - - - - - - - -| |
|
|
| rxdata (8 bit) (ro) | /
|
|
0x00000800 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
|
|
|
|
- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
|
|
|
|
0x00000800 ---32-----------16|15------------0-
|
|
| : | \
|
|
| : | |
|
|
GERMS | : | > CFG_NIOS_CPU_ROM_SIZE
|
|
| : | | = 0x00000800
|
|
| : | /
|
|
0x00000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
|
|
0x00000000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE
|
|
|
|
|
|
===============================================================================
|
|
F L A S H M E M O R Y A L L O C A T I O N
|
|
===============================================================================
|
|
|
|
0x01800000 ---8-------------4|3-------------0-
|
|
| : | \
|
|
| : | |
|
|
| : | > 6 MByte ROM FS
|
|
| : | |
|
|
| : | /
|
|
0x01200000 --+- - - - - - - -:- - - - - - - -+- - file system image(s)
|
|
| : | \
|
|
| : | |
|
|
| : | > 1728 kByte ucLinux
|
|
| : | |
|
|
| : | /
|
|
0x01050000 --+- - - - - - - -:- - - - - - - -+- - os image(s)
|
|
| : | \
|
|
0x01040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment
|
|
| : | |
|
|
| : | > 320 kByte U-Boot
|
|
| : | |
|
|
| : | |
|
|
| : | /
|
|
0x01000000 --+- - - - - - - -:- - - - - - - -+- - u-boot _start()
|
|
0x01000000 ---8-------------4|3-------------0-
|
|
|
|
|
|
===============================================================================
|
|
R E F E R E N C E S
|
|
===============================================================================
|
|
[1] http://www.altera.com/literature/ds/ds_nios_uart.pdf
|
|
[2] http://www.altera.com/literature/ds/ds_nios_timer.pdf
|
|
[3] http://www.altera.com/literature/ds/ds_nios_pio.pdf
|
|
[4] http://www.altera.com/literature/ds/ds_nios_spi.pdf
|
|
[5] http://www.t13.org/index.html
|
|
|
|
|
|
===============================================================================
|
|
Stephan Linz <linz@li-pro.net>
|