mirror of
https://github.com/AsahiLinux/u-boot
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49958813e2
The deadline for DM_USB migration has passed and all users have been migrated. Remove now unused code. Signed-off-by: Tom Rini <trini@konsulko.com>
328 lines
8.6 KiB
C
328 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <log.h>
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#include <usb.h>
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#include <errno.h>
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#include <linux/compiler.h>
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#include <linux/delay.h>
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#include <usb/ehci-ci.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <dm.h>
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#include <power/regulator.h>
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#include "ehci.h"
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#define MX5_USBOTHER_REGS_OFFSET 0x800
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#define MXC_OTG_OFFSET 0
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#define MXC_H1_OFFSET 0x200
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#define MXC_H2_OFFSET 0x400
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#define MXC_H3_OFFSET 0x600
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#define MXC_USBCTRL_OFFSET 0
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#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
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#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
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#define MXC_USB_CTRL_1_OFFSET 0x10
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#define MXC_USBH2CTRL_OFFSET 0x14
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#define MXC_USBH3CTRL_OFFSET 0x18
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/* USB_CTRL */
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/* OTG wakeup intr enable */
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#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
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/* OTG power mask */
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#define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
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/* OTG power pin polarity */
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#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
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/* Host1 ULPI interrupt enable */
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#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
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/* HOST1 wakeup intr enable */
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#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
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/* HOST1 power mask */
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#define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
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/* HOST1 power pin polarity */
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#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
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/* USB_PHY_CTRL_FUNC */
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/* OTG Polarity of Overcurrent */
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#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
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/* OTG Disable Overcurrent Event */
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#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
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/* UH1 Polarity of Overcurrent */
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#define MXC_H1_OC_POL_BIT (1 << 6)
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/* UH1 Disable Overcurrent Event */
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#define MXC_H1_OC_DIS_BIT (1 << 5)
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/* OTG Power Pin Polarity */
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#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
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/* USBH2CTRL */
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#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
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#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
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#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
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#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
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#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
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#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
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/* USBH3CTRL */
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#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
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#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
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#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
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#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
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#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
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/* USB_CTRL_1 */
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#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
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int mxc_set_usbcontrol(int port, unsigned int flags)
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{
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unsigned int v;
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void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
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void __iomem *usbother_base;
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int ret = 0;
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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switch (port) {
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case 0: /* OTG port */
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if (flags & MXC_EHCI_INTERNAL_PHY) {
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v = __raw_readl(usbother_base +
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MXC_USB_PHY_CTR_FUNC_OFFSET);
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if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
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v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
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else
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v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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/* OC/USBPWR is used */
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v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
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else
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/* OC/USBPWR is not used */
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v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
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#ifdef CONFIG_MX51
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
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else
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v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
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#endif
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__raw_writel(v, usbother_base +
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MXC_USB_PHY_CTR_FUNC_OFFSET);
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v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
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#ifdef CONFIG_MX51
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_OTG_UCTRL_OPM_BIT;
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else
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v |= MXC_OTG_UCTRL_OPM_BIT;
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#endif
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#ifdef CONFIG_MX53
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
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else
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v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
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#endif
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__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
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}
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break;
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case 1: /* Host 1 ULPI */
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#ifdef CONFIG_MX51
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/* The clock for the USBH1 ULPI port will come externally
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from the PHY. */
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v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
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__raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
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MXC_USB_CTRL_1_OFFSET);
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#endif
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v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
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#ifdef CONFIG_MX51
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
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else
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v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
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#endif
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#ifdef CONFIG_MX53
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
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else
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v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
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#endif
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__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
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v |= MXC_H1_OC_POL_BIT;
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else
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v &= ~MXC_H1_OC_POL_BIT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
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else
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v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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break;
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case 2: /* Host 2 ULPI */
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v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
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#ifdef CONFIG_MX51
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
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else
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v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
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#endif
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#ifdef CONFIG_MX53
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if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
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v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
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else
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v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
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else
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v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
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else
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v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
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#endif
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__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
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break;
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#ifdef CONFIG_MX53
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case 3: /* Host 3 ULPI */
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v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
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if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
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v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
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else
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v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
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else
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v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
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else
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v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
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__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
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break;
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#endif
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}
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return ret;
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}
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int __weak board_ehci_hcd_init(int port)
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{
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return 0;
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}
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void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
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{
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}
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__weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
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uint32_t *reg)
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{
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mdelay(50);
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}
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struct ehci_mx5_priv_data {
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struct ehci_ctrl ctrl;
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struct usb_ehci *ehci;
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struct udevice *vbus_supply;
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enum usb_init_type init_type;
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int portnr;
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};
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static const struct ehci_ops mx5_ehci_ops = {
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.powerup_fixup = mx5_ehci_powerup_fixup,
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};
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static int ehci_usb_of_to_plat(struct udevice *dev)
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{
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struct usb_plat *plat = dev_get_plat(dev);
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const char *mode;
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mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
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if (mode) {
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if (strcmp(mode, "peripheral") == 0)
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plat->init_type = USB_INIT_DEVICE;
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else if (strcmp(mode, "host") == 0)
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plat->init_type = USB_INIT_HOST;
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else
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return -EINVAL;
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}
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return 0;
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}
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static int ehci_usb_probe(struct udevice *dev)
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{
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struct usb_plat *plat = dev_get_plat(dev);
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struct usb_ehci *ehci = dev_read_addr_ptr(dev);
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struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
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enum usb_init_type type = plat->init_type;
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struct ehci_hccr *hccr;
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struct ehci_hcor *hcor;
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int ret;
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set_usboh3_clk();
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enable_usboh3_clk(true);
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set_usb_phy_clk();
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enable_usb_phy1_clk(true);
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enable_usb_phy2_clk(true);
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mdelay(1);
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priv->ehci = ehci;
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priv->portnr = dev_seq(dev);
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priv->init_type = type;
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ret = device_get_supply_regulator(dev, "vbus-supply",
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&priv->vbus_supply);
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if (ret)
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debug("%s: No vbus supply\n", dev->name);
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if (!ret && priv->vbus_supply) {
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ret = regulator_set_enable(priv->vbus_supply,
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(type == USB_INIT_DEVICE) ?
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false : true);
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if (ret) {
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puts("Error enabling VBUS supply\n");
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return ret;
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}
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}
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hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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hcor = (struct ehci_hcor *)((uint32_t)hccr +
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HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
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setbits_le32(&ehci->usbmode, CM_HOST);
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__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
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mdelay(10);
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return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
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priv->init_type);
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}
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static const struct udevice_id mx5_usb_ids[] = {
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{ .compatible = "fsl,imx53-usb" },
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{ }
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};
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U_BOOT_DRIVER(usb_mx5) = {
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.name = "ehci_mx5",
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.id = UCLASS_USB,
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.of_match = mx5_usb_ids,
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.of_to_plat = ehci_usb_of_to_plat,
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.probe = ehci_usb_probe,
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.remove = ehci_deregister,
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.ops = &ehci_usb_ops,
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.plat_auto = sizeof(struct usb_plat),
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.priv_auto = sizeof(struct ehci_mx5_priv_data),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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