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https://github.com/AsahiLinux/u-boot
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59d4230429
The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
137 lines
3.4 KiB
C
137 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _FIREWALL_H_
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#define _FIREWALL_H_
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#include <linux/bitops.h>
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struct socfpga_firwall_l4_per {
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u32 nand; /* 0x00 */
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u32 nand_data;
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u32 _pad_0x8;
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u32 usb0;
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u32 usb1; /* 0x10 */
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u32 _pad_0x14;
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u32 _pad_0x18;
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u32 spim0;
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u32 spim1; /* 0x20 */
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u32 spis0;
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u32 spis1;
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u32 emac0;
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u32 emac1; /* 0x30 */
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u32 emac2;
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u32 _pad_0x38;
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u32 _pad_0x3c;
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u32 sdmmc; /* 0x40 */
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u32 gpio0;
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u32 gpio1;
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u32 _pad_0x4c;
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u32 i2c0; /* 0x50 */
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u32 i2c1;
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u32 i2c2;
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u32 i2c3;
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u32 i2c4; /* 0x60 */
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u32 timer0;
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u32 timer1;
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u32 uart0;
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u32 uart1; /* 0x70 */
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};
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struct socfpga_firwall_l4_sys {
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u32 _pad_0x00; /* 0x00 */
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u32 _pad_0x04;
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u32 dma_ecc;
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u32 emac0rx_ecc;
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u32 emac0tx_ecc; /* 0x10 */
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u32 emac1rx_ecc;
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u32 emac1tx_ecc;
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u32 emac2rx_ecc;
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u32 emac2tx_ecc; /* 0x20 */
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u32 _pad_0x24;
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u32 _pad_0x28;
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u32 nand_ecc;
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u32 nand_read_ecc; /* 0x30 */
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u32 nand_write_ecc;
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u32 ocram_ecc;
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u32 _pad_0x3c;
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u32 sdmmc_ecc; /* 0x40 */
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u32 usb0_ecc;
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u32 usb1_ecc;
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u32 clock_manager;
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u32 _pad_0x50; /* 0x50 */
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u32 io_manager;
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u32 reset_manager;
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u32 system_manager;
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u32 osc0_timer; /* 0x60 */
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u32 osc1_timer;
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u32 watchdog0;
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u32 watchdog1;
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u32 watchdog2; /* 0x70 */
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u32 watchdog3;
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};
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#define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16))
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#define FIREWALL_BRIDGE_DISABLE_ALL (~0)
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/* Cache coherency unit (CCU) registers */
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#define CCU_CPU0_MPRT_ADBASE_DDRREG 0x4400
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0 0x45c0
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A 0x45e0
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B 0x4600
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C 0x4620
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D 0x4640
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E 0x4660
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#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0 0x4688
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE0 0x18560
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A 0x18580
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B 0x185a0
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C 0x185c0
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D 0x185e0
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E 0x18600
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#define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628
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#define CCU_TCU_MPRT_ADBASE_MEMSPACE0 0x2c520
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#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A 0x2c540
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#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B 0x2c560
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#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C 0x2c580
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#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D 0x2c5a0
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#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E 0x2c5c0
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#define CCU_ADMASK_P_MASK BIT(0)
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#define CCU_ADMASK_NS_MASK BIT(1)
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#define CCU_ADBASE_DI_MASK BIT(4)
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#define CCU_REG_ADDR(reg) \
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(SOCFPGA_CCU_ADDRESS + (reg))
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/* Firewall MPU DDR SCR registers */
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#define FW_MPU_DDR_SCR_EN 0x00
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#define FW_MPU_DDR_SCR_EN_SET 0x04
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#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE 0x10
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#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT 0x14
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#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT 0x18
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#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
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#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE 0x90
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#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT 0x94
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#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
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#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
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#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD 0xff
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#define MPUREGION0_ENABLE BIT(0)
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#define NONMPUREGION0_ENABLE BIT(8)
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#define FW_MPU_DDR_SCR_WRITEL(data, reg) \
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writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
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void firewall_setup(void);
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#endif /* _FIREWALL_H_ */
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