mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
a55014d09b
LTO (Link-Time Optimisation) is an very useful feature which can significantly reduce the size of U-Boot binaries. So far it has been made available for selected ARM boards and sandbox. However, incremental builds are much slower when LTO is used. For example, an incremental build of sandbox takes 2.1 seconds on my machine, but 6.7 seconds with LTO enabled. Add a NO_LTO parameter to the build, similar to NO_SDL, so it can be disabled during development if needed, for faster builds. Add some documentation about LTO while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
144 lines
3.1 KiB
C
144 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#ifndef __ASM_GBL_DATA_H
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#define __ASM_GBL_DATA_H
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#ifndef __ASSEMBLY__
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#include <config.h>
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#include <asm/types.h>
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#include <linux/types.h>
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/* Architecture-specific global data */
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struct arch_global_data {
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#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
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u32 sdhc_clk;
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#endif
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#if defined(CONFIG_FSL_ESDHC)
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u32 sdhc_per_clk;
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#endif
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#if defined(CONFIG_U_QE)
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u32 qe_clk;
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u32 brg_clk;
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uint mp_alloc_base;
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uint mp_alloc_top;
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#endif /* CONFIG_U_QE */
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#ifdef CONFIG_AT91FAMILY
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/* "static data" needed by at91's clock.c */
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unsigned long cpu_clk_rate_hz;
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unsigned long main_clk_rate_hz;
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unsigned long mck_rate_hz;
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unsigned long plla_rate_hz;
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unsigned long pllb_rate_hz;
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unsigned long at91_pllb_usb_init;
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#endif
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/* "static data" needed by most of timer.c on ARM platforms */
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unsigned long timer_rate_hz;
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unsigned int tbu;
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unsigned int tbl;
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unsigned long lastinc;
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unsigned long long timer_reset_value;
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#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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unsigned long tlb_addr;
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unsigned long tlb_size;
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#if defined(CONFIG_ARM64)
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unsigned long tlb_fillptr;
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unsigned long tlb_emerg;
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#endif
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#endif
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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#define MEM_RESERVE_SECURE_SECURED 0x1
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#define MEM_RESERVE_SECURE_MAINTAINED 0x2
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#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3)
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/*
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* Secure memory addr
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* This variable needs maintenance if the RAM base is not zero,
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* or if RAM splits into non-consecutive banks. It also has a
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* flag indicating the secure memory is marked as secure by MMU.
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* Flags used: 0x1 secured
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* 0x2 maintained
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*/
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phys_addr_t secure_ram;
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unsigned long tlb_allocated;
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#endif
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#ifdef CONFIG_RESV_RAM
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/*
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* Reserved RAM for memory resident, eg. Management Complex (MC)
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* driver which continues to run after U-Boot exits.
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*/
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phys_addr_t resv_ram;
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#endif
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#ifdef CONFIG_ARCH_OMAP2PLUS
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u32 omap_boot_device;
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u32 omap_boot_mode;
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u8 omap_ch_flags;
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#endif
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#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
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unsigned long mem2_clk;
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#endif
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#ifdef CONFIG_ARCH_IMX8
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struct udevice *scu_dev;
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#endif
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#ifdef CONFIG_IMX_SENTINEL
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struct udevice *s400_dev;
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u32 soc_rev;
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u32 lifecycle;
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u32 uid[4];
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#endif
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};
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#include <asm-generic/global_data.h>
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#if defined(__clang__) || defined(LTO_ENABLE)
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#define DECLARE_GLOBAL_DATA_PTR
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#define gd get_gd()
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static inline gd_t *get_gd(void)
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{
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gd_t *gd_ptr;
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#ifdef CONFIG_ARM64
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__asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr));
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#else
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__asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr));
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#endif
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return gd_ptr;
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}
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#else
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#ifdef CONFIG_ARM64
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#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18")
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#else
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#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9")
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#endif
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#endif
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static inline void set_gd(volatile gd_t *gd_ptr)
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{
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#ifdef CONFIG_ARM64
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__asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr));
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#elif __ARM_ARCH >= 7
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__asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr));
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#else
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__asm__ volatile("mov r9, %0\n" : : "r"(gd_ptr));
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#endif
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_GBL_DATA_H */
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