mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-24 16:32:20 +00:00
a38ed61643
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code, The set_wdog_reset() function is not necessary as this is handled by the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property being set. Signed-off-by: Peng Fan <peng.fan@nxp.com>
77 lines
1.4 KiB
C
77 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <linux/delay.h>
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#include <asm/global_data.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Enable RGMII TX clk output */
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setbits_le32(&gpr->gpr[1], BIT(22));
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}
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static int setup_eqos(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* set INTF as RGMII, enable RGMII TXC clock */
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clrsetbits_le32(&gpr->gpr[1],
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IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
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setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
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return set_clk_eqos(ENET_125MHZ);
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}
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#if CONFIG_IS_ENABLED(NET)
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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int ret = 0;
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if (CONFIG_IS_ENABLED(FEC_MXC)) {
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setup_fec();
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}
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if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) {
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ret = setup_eqos();
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}
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return ret;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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env_set("board_name", "EVK");
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env_set("board_rev", "iMX8MP");
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#endif
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return 0;
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}
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